Both ASIC and COT designs need the designer to fix the foundry at the onset. This is because the library and the design rules needed for both are supplied by the target foundry. COT, however, does have the flexibility for changing the foundry at a later stage provided the process is compatible across multiple foundries – however it still needs some verification to avoid problems on silicon. Multiple sources especially where one needs backups and also an advantage for price negotiations have been in the picture.
DFM does change a lot of value propositions. COT’s have been less costly not just because foundries compete on price but also because the extra service of design implementation in an ASIC comes with it’s own price tag. With DFM, the boundary between design and manufacturing is getting blurred and hence not many will opt for the traditional COT approach. Foundries will (and are) moving up in the design value chain.
With DFM, there is an increased need for foundries to share process information so that it’s taken into account during the design phase. Foundries collaborating with EDA vendors for this result into tools handling the yield issues while making it as transparent to the designer as possible. Design flows were devised and verified with specific tools (from single or multiple EDA vendors/sources) to tackle various design issues and facilitate FTSS. Now the verification of these flows includes another variable – foundry. i.e. a designer will need to know which foundry’s data has been used to verify the design flow before he starts using it.
Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty. There will be an economical need for them to see their foundries operate at capacity. For this, they will need to facilitate new designs in these technos; and hence they will be compelled to either share more information/collaborate or do every thing on it’s own i.e. a one stop shop.
Wednesday, December 21, 2005
Tuesday, December 13, 2005
TSMC executive sees more IP from foundry
To sell wafers, one needs tapeouts. Successful tapeouts require libraries and IPs validated on the target technology. And as technology advances, customers are more and more wary of getting their designs taped out with libraries and IPs not fully validated on silicon. So where does this lead a foundry with a ready advanced process but waiting for library & IP vendors to provide their wares on this new techno so that it can get customers’ designs in ?
Well, it provides libraries and IPs - either on it’s own or with partnerships. TSMC’s Europe Technical Director, Douglas Pattullo said in the IP/SoC conference in Grenoble on 7th Dec – TSMC is a provider not just of libraries but of complex IPs as well. He mentions that they are doing it to support their wafer manufacturing biz and not to get a new revenue stream.
It was once the same with EDA vendors. Quite a few of them started providing an IP portfolio – yes, to support their EDA biz. After all, customers are more comfortable with 3rd party IPs proven to be working in a specific design flow. But then as the process world started getting interleaved with the design world & the design space became abuzz with terms like DFM, DFY etc., the impact of foundry information on the EDA and IP space gained further importance.
So, are we headed towards a landscape dominated by a few major players (with deep pockets & partnerships) sporting One-Stop-Shops & dotted by smaller players excelling in niche areas say point EDA tools, special IPs ?
Well, it provides libraries and IPs - either on it’s own or with partnerships. TSMC’s Europe Technical Director, Douglas Pattullo said in the IP/SoC conference in Grenoble on 7th Dec – TSMC is a provider not just of libraries but of complex IPs as well. He mentions that they are doing it to support their wafer manufacturing biz and not to get a new revenue stream.
It was once the same with EDA vendors. Quite a few of them started providing an IP portfolio – yes, to support their EDA biz. After all, customers are more comfortable with 3rd party IPs proven to be working in a specific design flow. But then as the process world started getting interleaved with the design world & the design space became abuzz with terms like DFM, DFY etc., the impact of foundry information on the EDA and IP space gained further importance.
So, are we headed towards a landscape dominated by a few major players (with deep pockets & partnerships) sporting One-Stop-Shops & dotted by smaller players excelling in niche areas say point EDA tools, special IPs ?
Monday, December 05, 2005
Bring on 2006
Mentors' CEO Walden Rhines' interview in Electronic Times (posted on 2/12/05) brought out 2 interesting points in the EDA industry :
First is on the EDA industry growth which Rhines attributes mainly to developing new solutions to new problems, developing new methodologies & applying technology to different applications. With a very small growth in the number of designers and with tools and methodology in place, design companies do not tend to spend so much in purchasing that many new licenses/seats.
The second interesting point is about start-ups. Usually started by professionals from the major EDA companies/design companies when they see issues/loops in the design flow which they feel they can plug in much better than the existing tools. With the market growing more and more towards point tools and now towards an open platform, they focus on a niche issue. While they contribute a little over 20% of the market revenue, they do represent a major chunk of the EDA methodologies mindshare. And excepting a few of them who have a solid business plan in addition to the strong technology base, most get acquired by the major EDA companies - and spur their growth.
First is on the EDA industry growth which Rhines attributes mainly to developing new solutions to new problems, developing new methodologies & applying technology to different applications. With a very small growth in the number of designers and with tools and methodology in place, design companies do not tend to spend so much in purchasing that many new licenses/seats.
The second interesting point is about start-ups. Usually started by professionals from the major EDA companies/design companies when they see issues/loops in the design flow which they feel they can plug in much better than the existing tools. With the market growing more and more towards point tools and now towards an open platform, they focus on a niche issue. While they contribute a little over 20% of the market revenue, they do represent a major chunk of the EDA methodologies mindshare. And excepting a few of them who have a solid business plan in addition to the strong technology base, most get acquired by the major EDA companies - and spur their growth.
Monday, November 28, 2005
Cisco turns to ZTE in China
While most other competitors foresee more growth in China, Cisco sees an edge in India and is investing heavily there. The things going for India include an unregulated economy, less competitive environment & a growing market . It’s worries in China include weaker IP protection laws and an edge to home grown local companies like Huawei, Harbor Networks etc. through loans and government support.
The Cisco-ZTE co-operation agreement will let Cisco take advantage of ZTE’s position in the local service provider market and it’s customer knowledge.
The Cisco-ZTE co-operation agreement will let Cisco take advantage of ZTE’s position in the local service provider market and it’s customer knowledge.
Tuesday, November 22, 2005
More on DFM....
I read this paper, “Yield challenges require new DFM approach” by P.T Patel in EE Times. It’s very well written and informative.
Yet another pointer to making the existing design tools (the focus in the article was on routing) more suitable for getting your design manufacturable.
Yet another pointer to making the existing design tools (the focus in the article was on routing) more suitable for getting your design manufacturable.
Monday, November 21, 2005
Can someone explain DFM ?
Quite an interesting article in Electronic Engineering Times by Richard Goering.
Getting to basics ….
In commercial space, a designer designs a chip with the objective that it should not only function as per specs but also be manufactured in a commercially viable mode. This is implicit. Else shouldn’t we have heard about tools like Design for Silicon Success/DFSS or DFFTSS….??
Yes, we do have flows which aim for FTSS but not point tools. The point tools facilitate various design phases like simulation, synthesis, routing etc. but it’s a design flow which optimizes their usage to achieve objectives like intended functionality , high yield. In fact, all the existing design tools should have this “DFM” embedded in them by default.
Designers need not become manufacturing experts and the tools should be good enough to handle the yield issues in a transparent and automatic manner. But with the mandatory breaking of walls between design and manufacturing in the DSM zone, it does help for the designer to be aware of the potential manufacturing issues and take them into account while designing in order to avoid corrections at later stages.
Getting to basics ….
In commercial space, a designer designs a chip with the objective that it should not only function as per specs but also be manufactured in a commercially viable mode. This is implicit. Else shouldn’t we have heard about tools like Design for Silicon Success/DFSS or DFFTSS….??
Yes, we do have flows which aim for FTSS but not point tools. The point tools facilitate various design phases like simulation, synthesis, routing etc. but it’s a design flow which optimizes their usage to achieve objectives like intended functionality , high yield. In fact, all the existing design tools should have this “DFM” embedded in them by default.
Designers need not become manufacturing experts and the tools should be good enough to handle the yield issues in a transparent and automatic manner. But with the mandatory breaking of walls between design and manufacturing in the DSM zone, it does help for the designer to be aware of the potential manufacturing issues and take them into account while designing in order to avoid corrections at later stages.
Friday, November 18, 2005
Is Infineon going fabless ?
One of the potential solutions in addressing the challenges in manufacturing sub 90nm is in greater collaboration. How many of the existing top semiconductor companies can afford to be profitable while keeping their legs in both chip design as well as optimal yield DSM manufacturing ? One needs to focus upon ones’ strengths while leveraging with ones’ partners on others. Partnerships are extending; it’s a need & not just an option.
It makes me reflect on an article posted in Silicon Strategies on 12/27/2004, “15 predictions for IC, equipment biz in 2005 and beyond” which had a compilation of 15 predictions for the IC and chip-equipment industries in 2005 and beyond and listed some foundry marriages.
The sifting is being done……..
It makes me reflect on an article posted in Silicon Strategies on 12/27/2004, “15 predictions for IC, equipment biz in 2005 and beyond” which had a compilation of 15 predictions for the IC and chip-equipment industries in 2005 and beyond and listed some foundry marriages.
The sifting is being done……..
Monday, November 14, 2005
Unshackled IBM Microelectronics savors Game Box wins
Unshackled IBM Microelectronics savors Game Box wins - a very interesting article by Ed Sperling in a special report, Movers & Shakers 2005, in Electronic Business online.
Lining up 3 top gaming platforms, Sony PlayStation 3, Microsoft Xbox 360 and the follow on to the Nintendo GameCube as customers for it’s Cell Processor is a real volume play. In the absence of any real killer application, high volumes design wins do not come easy.
Steven Longoria, vice president of semiconductor technology platforms in IBM's Systems and Technology Group mentions that getting it’s technology consistent to avoid repetition of development steps is IBM’s top priority.
This is one area in the industry which usually takes a backseat amongst other priorities and is a major cause of ASIC design re spins. With the high mask costs, FTSS is getting more & more significant thus putting an ASIC vendor with a good track record of FTSS higher on the ASIC clients’ list. The shrinking market windows also do not leave much room for re spins.
Lining up 3 top gaming platforms, Sony PlayStation 3, Microsoft Xbox 360 and the follow on to the Nintendo GameCube as customers for it’s Cell Processor is a real volume play. In the absence of any real killer application, high volumes design wins do not come easy.
Steven Longoria, vice president of semiconductor technology platforms in IBM's Systems and Technology Group mentions that getting it’s technology consistent to avoid repetition of development steps is IBM’s top priority.
This is one area in the industry which usually takes a backseat amongst other priorities and is a major cause of ASIC design re spins. With the high mask costs, FTSS is getting more & more significant thus putting an ASIC vendor with a good track record of FTSS higher on the ASIC clients’ list. The shrinking market windows also do not leave much room for re spins.
Indian design activity on fast track, says iSuppli
Market research company, iSuppli Corp noted in a recent article posted in Electronic Engineering Times by Peter Clarke that India’s semiconductor design industry will nearly triple by 2010; it’s predicted to be 624M$ in ’05.
Investment in India needs to be for a long term strategic reason. Companies jumping into the bandwagon solely for cost reduction will most likely lose out. Some of the very factors driving the growth of the semiconductor industry here e.g. low cost design talent, strong education infrastructure and rapidly growing local market lead to challenges like high attrition rate. While money is a major factor for employee retention, career growth conducive work environment with interesting & innovative work on latest technology will help.
The other challenge of lack of trained designers is being addressed by the industry along with academia leading to several training start-ups which deliver mid & short term courses for fresh engineering graduates as well as working executives for VLSI careers.
Investment in India needs to be for a long term strategic reason. Companies jumping into the bandwagon solely for cost reduction will most likely lose out. Some of the very factors driving the growth of the semiconductor industry here e.g. low cost design talent, strong education infrastructure and rapidly growing local market lead to challenges like high attrition rate. While money is a major factor for employee retention, career growth conducive work environment with interesting & innovative work on latest technology will help.
The other challenge of lack of trained designers is being addressed by the industry along with academia leading to several training start-ups which deliver mid & short term courses for fresh engineering graduates as well as working executives for VLSI careers.
Monday, November 07, 2005
Panelists ponder challenges at 45 nm
The volumes need to justify the high costs involved in 45 nm. Costs include the mask cost (with 2 M$ not being ruled out), design challenges, variability & yield issues to count a few. The consumer market is the major drive for cost reduction and high volumes. However, it needs to be kept in mind that the market windows in this segment are shrinking. To capitalize on these high volumes, chip vendors need to be nimble enough to get the 45 nm product out in time – a feat which is getting tougher as one scales down in the DSM zone.
As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.
Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.
No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.
Excessive guardbanding should not cut back the gains arising from the scaling to this technology.
As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..
As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.
Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.
No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.
Excessive guardbanding should not cut back the gains arising from the scaling to this technology.
As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..
Friday, November 04, 2005
Moore's Law
The microelectronics industry owes much to Moore’s Law – the number of transistors on a chip double every 2 years. It’s a principle which has been solid and consistent for the last 3 decades.
In an article posted by Bill Roberts in Electronic Business, Satoru Ito, CEO of Renesas Technology says. "Because of Moore's Law, the industry has had a common road map for technological innovation. This allows partnerships and planning for investment."
It’s an economic barometer with geometric scaling transforming to economic scaling.
Moore’s Law has led to partnership. For no single entity, no matter how deep it’s pockets are and how well entrenched it is with brain power, can work out on it’s own the complexities in the microelectronics ecosystem paved by this law.
It has led to specialization. Semiconductor equipment materials, foundries, EDA, Contract manufacturing, IPs, yield management processes – it has spawned them all. It has spurred entrepreneurial culture without which technology’s potential could not have been realized. And with specialization and innovation not recognizing any geographical boundaries, it has further led to globalization. Biz interests make you go where there is infrastructure, cost saving, brain power, innovation – strategy reason. Moore’s law has sustained because it’s driven by pure economics. Geometric scaling is a prelude to diminishing the cost.
And it has also led to the omnipresent question - after Moore's Law, what ???
In an article posted by Bill Roberts in Electronic Business, Satoru Ito, CEO of Renesas Technology says. "Because of Moore's Law, the industry has had a common road map for technological innovation. This allows partnerships and planning for investment."
It’s an economic barometer with geometric scaling transforming to economic scaling.
Moore’s Law has led to partnership. For no single entity, no matter how deep it’s pockets are and how well entrenched it is with brain power, can work out on it’s own the complexities in the microelectronics ecosystem paved by this law.
It has led to specialization. Semiconductor equipment materials, foundries, EDA, Contract manufacturing, IPs, yield management processes – it has spawned them all. It has spurred entrepreneurial culture without which technology’s potential could not have been realized. And with specialization and innovation not recognizing any geographical boundaries, it has further led to globalization. Biz interests make you go where there is infrastructure, cost saving, brain power, innovation – strategy reason. Moore’s law has sustained because it’s driven by pure economics. Geometric scaling is a prelude to diminishing the cost.
And it has also led to the omnipresent question - after Moore's Law, what ???
India to take stake in fab project
It’s heartening to note Indian government’s proactive stance in putting India’s footprint on the hardware arena too. Several multinationals have a design/R&D setup in India. While most initially came for the comparatively cheap manpower, they’ve stayed put for the brain power and are now investing for innovation. Several local services and product companies too have sprung up. But what has been lacking is an efficient semiconductor manufacturing base i.e. fabs & testing entities. Developing and sustaining them is a formidable task as it’s an extremely capital (& commitment) intensive zone.
Taiwan’s ITRI is a good example to follow in guiding the technological and economic growth of the country. ITRI lists establishing new High tech industry, upgrading traditional industries, leading the drive for sustainable growth and developing highly skilled human resources under their industrial impact. It has played a vital role in turning this island state into a semiconductor hub housing world’s top two foundries and boasting of highly skilled designers.
Taiwan’s ITRI is a good example to follow in guiding the technological and economic growth of the country. ITRI lists establishing new High tech industry, upgrading traditional industries, leading the drive for sustainable growth and developing highly skilled human resources under their industrial impact. It has played a vital role in turning this island state into a semiconductor hub housing world’s top two foundries and boasting of highly skilled designers.
Wednesday, November 02, 2005
IBM backs VCs, startups to pursue platform aims
IBMs’ VC Group’s strategy outlines a varying and rewarding approach to the functioning of a ventures capital arm of a large company. Deviating from the well trodden path of investing cash for ROI, it is emphasizing more on relationships, interests’ alignment and development of a mutually supported ecosystem.
As IBM Corp. VP & MD of it’s VC group, Claudia Fan Munce, stresses in an article in EE Times, the access IBM gains to companies in emerging technos and geographies is worth much more than the return on the cash itself. IBM’s involvement with VC firms and startups aids it in setting it’s technology agenda and pushing it through.
Especially in Asian countries where the right networking/connections building (or guanxi as is called in Chinese) is so important for biz growth, this strategy looks more effective than the relatively “cold” dollars vs return.
As IBM Corp. VP & MD of it’s VC group, Claudia Fan Munce, stresses in an article in EE Times, the access IBM gains to companies in emerging technos and geographies is worth much more than the return on the cash itself. IBM’s involvement with VC firms and startups aids it in setting it’s technology agenda and pushing it through.
Especially in Asian countries where the right networking/connections building (or guanxi as is called in Chinese) is so important for biz growth, this strategy looks more effective than the relatively “cold” dollars vs return.
Consumer Era gives birth to "Gigafabs"
With consumer electronics joining PCs and internet based communications as a major semiconductor industry driver, fabs are getting into another league – Gigafabs. TSMC’s Mark Liu differentiates between the fabs on the basis of monthly wafers capacity – 80 to100K qualify as gigafabs while megafabs have a run rate of 50k wafers.
Consumer electronics market has a very short market window including a steep ramp up and leaves little room for redesigns. High price elasticity ranges encompass some real high priced niche products on one end and basic generic commodity tagged products on the other – and both categories can lead to massive volumes if the timing/placing-features-price combo target is hit.
Gigafabs help here because no vendor would like to be placed in a position where he has hit the market with the right product at the right time only to run out of fab capacity – a major biz opportunity loss. Also chips produced cheaper in the fabs (an advantage of gigafabs) can be sold cheaper. While gigafabs help to spread out the costs, not all players can join in due to the high costs involved.
Consumer electronics market has a very short market window including a steep ramp up and leaves little room for redesigns. High price elasticity ranges encompass some real high priced niche products on one end and basic generic commodity tagged products on the other – and both categories can lead to massive volumes if the timing/placing-features-price combo target is hit.
Gigafabs help here because no vendor would like to be placed in a position where he has hit the market with the right product at the right time only to run out of fab capacity – a major biz opportunity loss. Also chips produced cheaper in the fabs (an advantage of gigafabs) can be sold cheaper. While gigafabs help to spread out the costs, not all players can join in due to the high costs involved.
Monday, October 24, 2005
Warner to back Blu-ray and HD-DVD format
The latest in the battle for the new high definition DVD standard – Warner to back Blu-ray and HD-DVD format. Warner Bros. Entertainment, till now a key HD-DVD backer among the Hollywood studios announced that it’ll release films on Blu-ray format too.
The recent issue of Business Week has a very well written article giving the synopsis of the struggles in this standard.
The key entities in this format war are:
A. Consumer Electronics
1. Sony has a lot at stake in this standard. It’s a triple gain for them if Blu-ray becomes the industry format:
- Royalties from sale of all the Blu-ray disks sold
- Resurgence in it’s movie biz through DVD sales
- High sales in electronic gear (HDTVs, movie cameras, Blu-ray optical drives and most importantly – it’s new PlayStation game consoles which will include a Blu-ray drive for playing movies
2. Toshiba would like to continue the inflow of royalty payments coming from it’s current DVDs through it’s HD-DVD patents.
3. Others : HDTV and DVD drive makers
B. Media
With Warner supporting Blu-ray format too, the Sony camp has now 5 of 6 film studios. Sony’s safeguards developed to prevent Blu-ray movies from being ripped to a computer’s hard drive strengthened support for it’s format from the studios.
C. PC industry
1. Microsoft, Intel : They stand a lot to gain if PC were to emerge as a hub for digital entertainment. Microsoft has an additional issue – game console war with Sony. While Microsoft had decided to hold down costs by not including a next generation DVD player in the Xbox console (and instead stream HD content from a PC to a console which could be attached to a TV), Sony said that it’ll include Blu-ray in the next PlayStation game console beginning next year. Plus it decided not to use Microsoft’s iHD technology to add interactive features to Blu-ray disks, opting instead for Java based technology. Microsoft says that Blu-rays disks will be more expensive to manufacture; others do not see any big cost difference.
Both Microsoft and Intel back Toshiba’s HD-DVD format.
2. Dell, HP, Apple: They back Blu-ray. Dell and HP sell HDTVs too.
In an attempt to bridge the gap between the two formats, HP has recently urged the other Blu-ray members to support 2 key technologies (currently supported in HD-DVD): Managed Copy (lets users make legitimate copies of their HD movies) and iHD (Microsoft’s techno for interactive features).
There looks to be only 1 winner.........
The recent issue of Business Week has a very well written article giving the synopsis of the struggles in this standard.
The key entities in this format war are:
A. Consumer Electronics
1. Sony has a lot at stake in this standard. It’s a triple gain for them if Blu-ray becomes the industry format:
- Royalties from sale of all the Blu-ray disks sold
- Resurgence in it’s movie biz through DVD sales
- High sales in electronic gear (HDTVs, movie cameras, Blu-ray optical drives and most importantly – it’s new PlayStation game consoles which will include a Blu-ray drive for playing movies
2. Toshiba would like to continue the inflow of royalty payments coming from it’s current DVDs through it’s HD-DVD patents.
3. Others : HDTV and DVD drive makers
B. Media
With Warner supporting Blu-ray format too, the Sony camp has now 5 of 6 film studios. Sony’s safeguards developed to prevent Blu-ray movies from being ripped to a computer’s hard drive strengthened support for it’s format from the studios.
C. PC industry
1. Microsoft, Intel : They stand a lot to gain if PC were to emerge as a hub for digital entertainment. Microsoft has an additional issue – game console war with Sony. While Microsoft had decided to hold down costs by not including a next generation DVD player in the Xbox console (and instead stream HD content from a PC to a console which could be attached to a TV), Sony said that it’ll include Blu-ray in the next PlayStation game console beginning next year. Plus it decided not to use Microsoft’s iHD technology to add interactive features to Blu-ray disks, opting instead for Java based technology. Microsoft says that Blu-rays disks will be more expensive to manufacture; others do not see any big cost difference.
Both Microsoft and Intel back Toshiba’s HD-DVD format.
2. Dell, HP, Apple: They back Blu-ray. Dell and HP sell HDTVs too.
In an attempt to bridge the gap between the two formats, HP has recently urged the other Blu-ray members to support 2 key technologies (currently supported in HD-DVD): Managed Copy (lets users make legitimate copies of their HD movies) and iHD (Microsoft’s techno for interactive features).
There looks to be only 1 winner.........
Wednesday, October 19, 2005
Design trends & EDA tools : China & Taiwan
I recently read the latest report from EE Times and Gartner Dataquest on Design Trends & EDA Tools : China & Taiwan. It can be accessed from their website http://www.eetasia.com.
The report makes a very interesting reading and made me ponder on a few points.......
The report makes a very interesting reading and made me ponder on a few points.......
ASIC Design segment
A. Application segment
While consumer applications remained the major application segment in Taiwan (as was in ’04 too), it displaced Telecom/Datacom in China to be the major one there too. Some possible underlying reasons (apart from generic market conditions) could be
· Telecom/Datacom designs have traditionally been using the leading edge process geometry. The rising mask costs associated with them could have been a factor of the decrease in new ASIC designs.
· The varied & vast set of categories within the consumer applications mkt. abets more ASIC designs and spin-offs.
· More consumer ASICs are coming out with the rapid growth of the China consumer mkt.
B. Gate Count
The general increase in the gate count follows the rising complexity which is also aided by the integration of various functions/categories in a single product.
Majority of the respondents working on large designs are companies that are local subsidiaries of foreign companies or local ventures – not joint ventures with foreign companies. This is mostly due to the high costs involved in large & complex designs. It makes sense for joint ventures with foreign companies to focus on the local marketing & enhance their foreign partner’s footprint in the local mkt.
C. Process Geometry
China figures indicate a more rapid embracing of newer technos.
The 0.18um in Taiwan, apart from remaining the predominant node for the past 3 years, has grown from 35% from last year to 44% while the 0.13um has increased from 13% to 23%.
0.18um is still the dominant node in China. However, it’s share has slightly decreased from 49% to 45%. But it’s in the 0.13um that we see the real increase – 12% to 31%
D. IP core usage rate
EDA companies’ share has decreased and has been correctly attributed to their partnering with foundries. With the increasing complexities and the focus going more towards Design for Yield, it is natural for foundries to play a major role in this partnership with EDA vendors/3rd party IP suppliers. The growing complexity of selecting the right IP & the subsequent issues seen during their integration in the design compel companies resort to developing them in-house. The marked surge in the independent 3rd party suppliers is also due the fact that they specialize in their niche IPs & these IPs are their main products.
EDA tools usage
Increasing reliability and reduced costs are the paramount factors for the electronic designers in Taiwan (increased functionality is no longer the most important goal) while increased functionality and reduced cost are the most important goals for the designers in China.
This possibly indicates a more mature market (in terms of EDA tools usage) in Taiwan where they seem to be more conversant and satisfied with the various functionality features offered by the EDA tools and hence are focusing more on reliability i.e. fewer issues while going through the design flow and hence shortening their time to market.
Cost reduction remains common; not surprising where Consumer applications is the predominant market.
Tuesday, October 11, 2005
Will Structured ASICs be successful ?
Comments on the above article (written by Vince Hopkins in Electronic News)........
Tweak a bit here and there for it’s derivatives, term it in various categories, yes, the bottom line is identical value propositions i.e. reduced NRE and faster time to market which have become critical factors in the transient markets and DSM technos.
So, one has variants: a 90% ready netlist which at least in concept can readily accept limited design changes as per multiple customer requirements and drastically reduce the design cycle time to semi fabricated design slices ready for custom metallization for final customer designs.
ASIC vendors providing both traditional ASIC (cell based) and Structured ASIC capabilities hold an added advantage for the customer if he does decide to transit later from structured to regular ASIC i.e. for higher volumes with cost reduction. Filling the gap of the mid range market, it’s given another option for customers sitting on the FPGA/ASIC fence.
Tweak a bit here and there for it’s derivatives, term it in various categories, yes, the bottom line is identical value propositions i.e. reduced NRE and faster time to market which have become critical factors in the transient markets and DSM technos.
So, one has variants: a 90% ready netlist which at least in concept can readily accept limited design changes as per multiple customer requirements and drastically reduce the design cycle time to semi fabricated design slices ready for custom metallization for final customer designs.
ASIC vendors providing both traditional ASIC (cell based) and Structured ASIC capabilities hold an added advantage for the customer if he does decide to transit later from structured to regular ASIC i.e. for higher volumes with cost reduction. Filling the gap of the mid range market, it’s given another option for customers sitting on the FPGA/ASIC fence.
Wednesday, October 05, 2005
UMC’s Hu envisions a new model for foundry business
Comments on “UMC’s Hu envisions a new model for foundry business” in Electronic Engineering Times by Ron Wilson
While it’s true that the leading foundries in this age must have the capabilities of an integrated device manufacturer, the transition from foundry to solutions provider is not an altogether new biz model nor is it an entirely different vision for foundry companies.
Quite a few years back, when foundries, especially in Taiwan, realized that low cost was no longer sufficient for their intended growth, they started focusing more on their IP portfolios. Design support also evolved into working on actual design issues and in some cases offering design services.
To cite a few……
TSMC offers IP portfolio, Design Centre Alliance, In house and 3rd party library services and Assembly & Testing services to some extent.
Chartered offers IP Access & Design Access.
Some are transitioning into this model with 3rd party collaboration while some try to develop it in-house. Foundries also hold an additional advantage in addressing DFM issues.
While it’s true that the leading foundries in this age must have the capabilities of an integrated device manufacturer, the transition from foundry to solutions provider is not an altogether new biz model nor is it an entirely different vision for foundry companies.
Quite a few years back, when foundries, especially in Taiwan, realized that low cost was no longer sufficient for their intended growth, they started focusing more on their IP portfolios. Design support also evolved into working on actual design issues and in some cases offering design services.
To cite a few……
TSMC offers IP portfolio, Design Centre Alliance, In house and 3rd party library services and Assembly & Testing services to some extent.
Chartered offers IP Access & Design Access.
Some are transitioning into this model with 3rd party collaboration while some try to develop it in-house. Foundries also hold an additional advantage in addressing DFM issues.
Saturday, October 01, 2005
ASIC makers piece together their options
Refering to "ASIC makers piece together their options" – Ron Wilson & Brian Fuller in EE Times
In an ideal world, the various entities i.e. Design company, foundry, EDA vendor, Packaging, Testing etc. will work together with the customer in a free information flow environment (albeit respecting each others IP rights). Bolstered by the information flow, they can provide collectively the customer with an optimal product (good design, good yield) whilst retaining their focus on their individual targets – and their bottom lines.
But, alas, it’s not the world we live in. And hence we see various strategies for surviving in this market - Fujitsu Microelectronics may be alleviating it’s new process risk costs by spreading it across it’s internal customers and LSI Logic by going fabless while sustaining itself on it’s excellent IP portfolio etc. – as cited in the article.
The partnership model between Chartered, IBM and Samsung will be interesting to watch - what with the potential of a customer being able to tape out with any of the 3 partners and then be able to select any of the 3 (not necessarily the same) as the foundry. How many ASIC semiconductor companies i.e. with both design & foundry capabilities, would be willing to go through the ASIC development only to see another company being chosen as the foundry ? ASICs are still taken up for their final revenues based on ASPs and not just the NREs. Or is this leading to supplementing of required know-how while possibly complementing on other skill-sets ??
In an ideal world, the various entities i.e. Design company, foundry, EDA vendor, Packaging, Testing etc. will work together with the customer in a free information flow environment (albeit respecting each others IP rights). Bolstered by the information flow, they can provide collectively the customer with an optimal product (good design, good yield) whilst retaining their focus on their individual targets – and their bottom lines.
But, alas, it’s not the world we live in. And hence we see various strategies for surviving in this market - Fujitsu Microelectronics may be alleviating it’s new process risk costs by spreading it across it’s internal customers and LSI Logic by going fabless while sustaining itself on it’s excellent IP portfolio etc. – as cited in the article.
The partnership model between Chartered, IBM and Samsung will be interesting to watch - what with the potential of a customer being able to tape out with any of the 3 partners and then be able to select any of the 3 (not necessarily the same) as the foundry. How many ASIC semiconductor companies i.e. with both design & foundry capabilities, would be willing to go through the ASIC development only to see another company being chosen as the foundry ? ASICs are still taken up for their final revenues based on ASPs and not just the NREs. Or is this leading to supplementing of required know-how while possibly complementing on other skill-sets ??
Monday, September 26, 2005
Freescale partners with Indian Design Houses
Comments on “Freescale partners with Indian Design Houses” by K.C Krishnadas in EE Times
This is indeed a strategy leading to multiple mutual benefits i.e. if implemented in the right spirit.
The right IP, the right technology, the optimal design flow, the right timing: neither of these factors can hold on their own in today’s volatile market. The customer wants a solution, not a set of leggo blocks left to him to assemble together.
Most of the design houses have some excellent design talent coupled with great technology, flow and ideas. But the present highly fragmented and transient market makes it very difficult for these design houses to even survive the initial few years before they hit the market and revenues start trickling in. The ruthless market conditions have led to the premature demise of many a promising design houses. With the multinationals tapping on these entities for domain know how and a basic solution using their IPs and the design houses leveraging on the multinationals’ clout (financial and market channels), it can be a win-win situation.
This is indeed a strategy leading to multiple mutual benefits i.e. if implemented in the right spirit.
The right IP, the right technology, the optimal design flow, the right timing: neither of these factors can hold on their own in today’s volatile market. The customer wants a solution, not a set of leggo blocks left to him to assemble together.
Most of the design houses have some excellent design talent coupled with great technology, flow and ideas. But the present highly fragmented and transient market makes it very difficult for these design houses to even survive the initial few years before they hit the market and revenues start trickling in. The ruthless market conditions have led to the premature demise of many a promising design houses. With the multinationals tapping on these entities for domain know how and a basic solution using their IPs and the design houses leveraging on the multinationals’ clout (financial and market channels), it can be a win-win situation.
Monday, September 19, 2005
Open-Silicon automates the flow
Refering to When infrastructure is essence: Open-Silicon automates the flow , an article posted in Electronic Engineering Times by Ron Wilson on Sep 16 2005
ASIC implementation is a complex procedure.
Automating it is more complex.
And adhering to the automated flow & achieving the intended results is an art in itself.
Every ASIC design team would have ventured into attempting to automate the complete process at least once in it’s life time. From my experience, it’s not the complexities involved (in the methodology or the automation), nor is it the lack of resources; but it is the good old discipline (or lack of it) that keeps one away from achieving the benefits of this automation. The biggest spoke in such an automation is the varied sets of designs, each with it’s unique baggage of complexities and requirements. Deviations are bound to occur if one needs each design to be optimized. So, it’s heartening to note that Open Silicon’s automated flow intends to include such creative detours.
It takes time (and restraint) to include all details; version control, detailed comments, personal tweaking, coding practices etc. I recollect the time when I had to put on hold all library releases by my team in order to include version control; it was not one of my favorite periods ! But yes, the subsequent gains more than supplemented for it.
Having developed, implemented as well as managed a gamut of automations across various ASIC implementations spanning various geographies, I adhere to the age old wisdom : A tool is as good as it’s implementation.
ASIC implementation is a complex procedure.
Automating it is more complex.
And adhering to the automated flow & achieving the intended results is an art in itself.
Every ASIC design team would have ventured into attempting to automate the complete process at least once in it’s life time. From my experience, it’s not the complexities involved (in the methodology or the automation), nor is it the lack of resources; but it is the good old discipline (or lack of it) that keeps one away from achieving the benefits of this automation. The biggest spoke in such an automation is the varied sets of designs, each with it’s unique baggage of complexities and requirements. Deviations are bound to occur if one needs each design to be optimized. So, it’s heartening to note that Open Silicon’s automated flow intends to include such creative detours.
It takes time (and restraint) to include all details; version control, detailed comments, personal tweaking, coding practices etc. I recollect the time when I had to put on hold all library releases by my team in order to include version control; it was not one of my favorite periods ! But yes, the subsequent gains more than supplemented for it.
Having developed, implemented as well as managed a gamut of automations across various ASIC implementations spanning various geographies, I adhere to the age old wisdom : A tool is as good as it’s implementation.
Friday, September 16, 2005
Taiwan as centre of IC world
Comments on “Seeing Taiwan as centre of IC world”, an interview of Nicky Lu by Mike Clendinin
IPs fill up the differentiating edge gap in a product leading to higher sales and thus higher revenues. But the broad definition of IP has also changed over the years. What was initially termed as the “winning” block in a chip has now become a generic part. So one needs to keep up innovating to come up with new IPs, new value-addition to the IC.
In the “manufacturing reigns supreme” years, Taiwan had the edge of having the wafer fab, assembly & testing plants as well as multiple design houses in the vicinity. Later when this along with the lower cost was no longer sufficient, foundries started focusing more on their IP portfolios and now on addressing the various issues arising in the design chain, in addition to the manufacturing issues. This has also been a triggered by the need of the “falling of the walls” between the design space and manufacturing space. Forced or not, this is good for the industry especially in the DSM zone.
Given the earlier edge of having in place the basic semiconductor ecosystem, Taiwan can be strongly poised if it can efficiently harness the synergy from it as an integral unit rather than as separate entities.
IPs fill up the differentiating edge gap in a product leading to higher sales and thus higher revenues. But the broad definition of IP has also changed over the years. What was initially termed as the “winning” block in a chip has now become a generic part. So one needs to keep up innovating to come up with new IPs, new value-addition to the IC.
In the “manufacturing reigns supreme” years, Taiwan had the edge of having the wafer fab, assembly & testing plants as well as multiple design houses in the vicinity. Later when this along with the lower cost was no longer sufficient, foundries started focusing more on their IP portfolios and now on addressing the various issues arising in the design chain, in addition to the manufacturing issues. This has also been a triggered by the need of the “falling of the walls” between the design space and manufacturing space. Forced or not, this is good for the industry especially in the DSM zone.
Given the earlier edge of having in place the basic semiconductor ecosystem, Taiwan can be strongly poised if it can efficiently harness the synergy from it as an integral unit rather than as separate entities.
Thursday, September 01, 2005
Leaky chips test designers' skills
Refering to Leaky chips test designers' skills by Mike Clendinin in www.eetasia.com
Yes, one can no longer rely upon deploying the power optimization techniques in the later part of the design. For that matter, it’s not sufficient to keep it restricted to any one design phase. It needs to be strategized and implemented right from algorithmic level, through architecture level and down to the placement & route phases. The higher the level, the more power savings one gets.
And there’s a constant balancing act between the various design constraints i.e. power, area and timing……..at least as of now.
Yes, one can no longer rely upon deploying the power optimization techniques in the later part of the design. For that matter, it’s not sufficient to keep it restricted to any one design phase. It needs to be strategized and implemented right from algorithmic level, through architecture level and down to the placement & route phases. The higher the level, the more power savings one gets.
And there’s a constant balancing act between the various design constraints i.e. power, area and timing……..at least as of now.
Monday, August 22, 2005
Are ESL and DFM false hopes ?
Refering to Are ESL and DFM false hopes? by Richard Goering in www.eetasia.com -
ESL and DFM are the two buzzwords in the DSM design space. With the spiraling costs involved, such techniques are getting into the mandatory zone. If we say that ESL is too domain and application specific, it’s just following another important trend in the market – that of structured ASICs/platform ASICs. You get master slices for various applications and these are further customized as per actual requirement. Is the industry, having moved from a “single EDA vendor toolset for a complete integrated design flow” to a “unified design flow integrated with various point tools from multiple EDA vendors” headed towards one with “point tools with a user defined interface for point customizations” ?
DFM surely requires a strong close link between the designer and the foundry but are the foundries ready for this ? The skyrocketing costs of setting up new fabs with the DSM processes led the foundries to partner together. Will the lure of acceptable yield and revenues henceforth get a similar result between IDMs and foundries ?
ESL and DFM are the two buzzwords in the DSM design space. With the spiraling costs involved, such techniques are getting into the mandatory zone. If we say that ESL is too domain and application specific, it’s just following another important trend in the market – that of structured ASICs/platform ASICs. You get master slices for various applications and these are further customized as per actual requirement. Is the industry, having moved from a “single EDA vendor toolset for a complete integrated design flow” to a “unified design flow integrated with various point tools from multiple EDA vendors” headed towards one with “point tools with a user defined interface for point customizations” ?
DFM surely requires a strong close link between the designer and the foundry but are the foundries ready for this ? The skyrocketing costs of setting up new fabs with the DSM processes led the foundries to partner together. Will the lure of acceptable yield and revenues henceforth get a similar result between IDMs and foundries ?
Wednesday, August 17, 2005
Advent of Program Management in ASIC implementation
ASICs started getting complex. Teams got globally dispersed. This was now no longer restricted to the foundries or the chip backend operations but also to the design team. Add to that a customer sitting in another location. To get a synergy across these islands of expertise for a FTSS moved Program Management role to a necessity. A necessity highlighted by the spiraling cost of design re-spins and exacerbated by the fragmented and transient market requirements.
From my experience, here are a few enablers for successful program implementation:
- Pro-active involvement right from the beginning i.e. from RFQ evaluation.
- Clear formulation of the specs mutually agreed and signed by both vendor and client. In this transient market, modifications are inevitable. However time spent in getting the basic set right is worthwhile.
- A well defined program schedule with clear allocation of resources and checklists
and it’s effective implementation. There are many software packages in the market; however keep in mind that a tool is as good as it’s implementation
- Effective communication
In my experience, lack of effective communication has been a major source of delays and issues cropping up in the program. Technical issues and logistic problems may be sorted out with a lesser impact. And it’s not just a language difference. Cultural and personality issues are not insignificant here. Effective documentation, a good rapport, increased presence, periodic meetings & regular updates, conference calls followed up by a written summary are a few enablers here.
- Anticipate and pre-empt issues and effective workarounds/solutions for problems
A good grasp of the complete ASIC supply chain provides an excellent leverage here. A good Program Manager can foresee the implications of decisions taken in a particular program phase, e.g. design on another phase e.g. packaging, on the ASIC program; a fact which may be lost on an engineer sitting in his island of expertise.
From my experience, here are a few enablers for successful program implementation:
- Pro-active involvement right from the beginning i.e. from RFQ evaluation.
- Clear formulation of the specs mutually agreed and signed by both vendor and client. In this transient market, modifications are inevitable. However time spent in getting the basic set right is worthwhile.
- A well defined program schedule with clear allocation of resources and checklists
and it’s effective implementation. There are many software packages in the market; however keep in mind that a tool is as good as it’s implementation
- Effective communication
In my experience, lack of effective communication has been a major source of delays and issues cropping up in the program. Technical issues and logistic problems may be sorted out with a lesser impact. And it’s not just a language difference. Cultural and personality issues are not insignificant here. Effective documentation, a good rapport, increased presence, periodic meetings & regular updates, conference calls followed up by a written summary are a few enablers here.
- Anticipate and pre-empt issues and effective workarounds/solutions for problems
A good grasp of the complete ASIC supply chain provides an excellent leverage here. A good Program Manager can foresee the implications of decisions taken in a particular program phase, e.g. design on another phase e.g. packaging, on the ASIC program; a fact which may be lost on an engineer sitting in his island of expertise.
Friday, July 29, 2005
PDA fad is over
Peter Clarke’s article PDA fad is over makes a compelling reading.
The appeal of the decreasing form factor in consumer gadgets made it’s advent not too long ago and was quickly embraced by the “young-on the move-possess-latest-gizmo” crowd. Along with came the expectation of packing of multiple features leading the industry to be perpetually kept on a delicate balancing act of features vs. size. And in features selection too, you have yet another formidable task. In the beginning, there were multiple gadget categories (you have a camera, a phone, an electronic diary etc.). But now you have a varying mix with blurred demarcations. The question that props up in the consumer’s mind is : do I go for a PDA phone or a phone PDA ?? A Blackberry is great for keeping me in sync with my email messages and to enforce my presence in this 24/365 flat world scenario, but how efficient is it to help me in calling and receiving telephone calls ?
And thus enters a plethora of gadgets, each with a dominant set of features catering to a specific market segment. It is difficult, if not impossible, to cater to all the transient and ever growing consumer requirements, into a handheld gadget with a long battery life and…. just to make life simpler “get the product out ASAP in market windows which are shrinking almost in line with the semiconductor process technology”! and I have not yet touched on pricing.
And that is where lies one of the major challenges : anticipating and gauging the consumer’s interests and preferences, getting the right mix (like Coke’s secret formula, but then even they were forced to innovate to sustain the consumers’ changing tastes!) and a continuous innovation (rather spin-offs from a basic model to be cost effective).
The appeal of the decreasing form factor in consumer gadgets made it’s advent not too long ago and was quickly embraced by the “young-on the move-possess-latest-gizmo” crowd. Along with came the expectation of packing of multiple features leading the industry to be perpetually kept on a delicate balancing act of features vs. size. And in features selection too, you have yet another formidable task. In the beginning, there were multiple gadget categories (you have a camera, a phone, an electronic diary etc.). But now you have a varying mix with blurred demarcations. The question that props up in the consumer’s mind is : do I go for a PDA phone or a phone PDA ?? A Blackberry is great for keeping me in sync with my email messages and to enforce my presence in this 24/365 flat world scenario, but how efficient is it to help me in calling and receiving telephone calls ?
And thus enters a plethora of gadgets, each with a dominant set of features catering to a specific market segment. It is difficult, if not impossible, to cater to all the transient and ever growing consumer requirements, into a handheld gadget with a long battery life and…. just to make life simpler “get the product out ASAP in market windows which are shrinking almost in line with the semiconductor process technology”! and I have not yet touched on pricing.
And that is where lies one of the major challenges : anticipating and gauging the consumer’s interests and preferences, getting the right mix (like Coke’s secret formula, but then even they were forced to innovate to sustain the consumers’ changing tastes!) and a continuous innovation (rather spin-offs from a basic model to be cost effective).
Wednesday, February 02, 2005
Welcome Me to Blogging World
This blog shall attempt to cover thoughts and ideas related to the VLSI Ecosystem
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