TSMC executive sees more IP from foundry

To sell wafers, one needs tapeouts. Successful tapeouts require libraries and IPs validated on the target technology. And as technology advances, customers are more and more wary of getting their designs taped out with libraries and IPs not fully validated on silicon. So where does this lead a foundry with a ready advanced process but waiting for library & IP vendors to provide their wares on this new techno so that it can get customers’ designs in ?

Well, it provides libraries and IPs - either on it’s own or with partnerships. TSMC’s Europe Technical Director, Douglas Pattullo said in the IP/SoC conference in Grenoble on 7th Dec – TSMC is a provider not just of libraries but of complex IPs as well. He mentions that they are doing it to support their wafer manufacturing biz and not to get a new revenue stream.

It was once the same with EDA vendors. Quite a few of them started providing an IP portfolio – yes, to support their EDA biz. After all, customers are more comfortable with 3rd party IPs proven to be working in a specific design flow. But then as the process world started getting interleaved with the design world & the design space became abuzz with terms like DFM, DFY etc., the impact of foundry information on the EDA and IP space gained further importance.

So, are we headed towards a landscape dominated by a few major players (with deep pockets & partnerships) sporting One-Stop-Shops & dotted by smaller players excelling in niche areas say point EDA tools, special IPs ?