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Common Platform Agreement extended to 32nm

IBM and its Common Platform agreement partners will extend their development relationship to 32nm too.

The group started with 2 partners – IBM and Chartered. This later included Infineon, Samsung, and now Freescale. In addition, with the collapse of Crolles Alliance, it can also draw more partners.

While collaboration is a necessity in these process nodes and the Common Platform Agreement has been doing quite well, there have been reports (which subsequently have been dismissed as rumours) that the foundry vendors in the alliance are struggling with compatibility issues - and this can get compounded with increasing number of members.

TSMC catches up with Intel on 45nm production

So, a foundry has closed the gap with an IDM!

In all likelihoods, TSMC will be in volume production for 45nm at the same time as Intel – in first half of 2008. As noted by David Manners in an an earlier post, “With all this third party expertise soaking up the industry’s value-add, where is there to go for the IDMs?”

TSMC makes IP but denies it is in IP business

Call it as seismic changes or consolidation, the chip manufacturing world is going through some upheaval. While on one end, quite a few IDMs are transitioning to a fab lite strategy (albeit in different flavours) - especially with the high costs & risks involved in sub 65nm, on the other end heavyweights like TSMC are spreading their reach into the IP arena too.

As I noted in an earlier post, TSMC is leveraging on its resources and market reach.It may start off as “strengthening the design collaboration for critical sub circuits” (who doesn’t want FTSS??) but the intensity of the move has been enough to spread ripples in the till now independent IP biz world. By doing so, TSMC may well be doing its share in mitigating some of the risks involved in DSM design and thus catalyzing more of these design starts; and subsequently fill up its high-end fabs.

STATS ChipPAC shareholders resist private equity buyout

In the recent spate of takeovers by the private equity world and at a time when the chip industry is undergoing consolidation, a blip has occurred – Temasek Holdings’ wholly owned subsidiary, Singapore Technologies Semiconductors Pte Ltd. (STSPL) has failed to complete its attempted buyout of test and assembly provider STATS ChipPAC Ltd. STSPL now has a majority stake of 83.1 percent in the company, falling short of the 90% required to make STATS ChipPAC completely private

Low power IC design kit enables representative design

Cadence is slated to release its Low Power Methodology Kit in late June. The highlight of the kit is a wireless "representative design" implemented using multi-supply voltage and power shutoff methods. It comes with all the necessary command scripts and technology files to complete the design. The design has sample IP including a processor and bus fabric from ARM, Wi-Fi from Wipro, USB 2.0 from ChipIdea, 65nm low-power memories from Virage Logic and 65nm technology libraries from TSMC.

While till date, EDA vendors have been mostly dishing out different point tools to address the industry’s power concerns, a big challenge is to help designers utilize the appropriate low power techniques and tools effectively and seamlessly within their flow on a real design – and in a timely manner. They need to be aware of the trade-offs required and some balancing tips to make the exercise productive.

A representative design is a step forward in this direction. The objective may be to regain the lead in the format war, but if it helps the end user, it definitely signals well!

Renesas seeks to keep its own process technology

Renesas seems to be bucking the trend of IDMs relying more and more on foundries for advanced process technology development.

Renesas believes in working (on its own or in collaboration) on advanced process development. With plans to increase sales in system-on-chip solutions and microcontrollers, it may make sense to keep the advanced process development in-house in order to have more control and direction for their major product offerings.

This, however, will not prevent it from outsourcing for volume production on advanced devices

TI takes two approaches to IC manufacturing

Mark LaPedus reports in his article in EETimes about TI’s approach towards IC manufacturing – while bolstering its in-house effort in analog production, TI is shifting more of its logic based work & process flow to foundries.

TI is adopting a 3 pronged approach based on its product categories - At the 65-nm node, TI has three foundry partners for its wireless chips: Chartered, TSMC and UMC. For wireless chips at 45 nm, TI will continue to use UMC and TSMC. For DSPs, TI develops the processes & makes its own 65nm DSP. However it will rope in TSMC too for the next node. TI has been manufacturing Sparc processors for Sun; a foundry, probably UMC, will take over production at 45nm.

Shifting the responsibility of digital processes to outside foundries, while focusing on analog processes for in-house manufacturing does seem to be the right direction, especially now when the production costs & risks are escalating. However, this is not an all together new approach. If I recollect well, STMicroelectronics had followed this approach along with TSMC. While the base/digital process was same across the two companies, STM developed its own spin-offs e.g. analog, high power, RF for and based on its market requirements.
The advantages are: risk sharing (in certain cases, offloading) in base process, retaining its niche in customized or spin-off processes and having the second source options when capacity is needed.

The article mentions that by using leading-edge foundries, fabless Qualcomm Inc. has been able to close the manufacturing gap with rival TI. I would say that it wasn’t just using leading edge foundries; it was close co-operation with multiple leading edge foundries coupled with the adoption of what it termed as Integrated Fabless Manufacturing Strategy (IFM) that helped Qualcomm. As I noted in my earlier post, "Fabless Qualcomm zooms to next node", (incidentally a comment on another article by the same author!) Qualcomm developed its own virtual manufacturing organization.

LSI Corp. may exit Consumer Electronics Biz

According to a news report, LSI Corp. is considering whether or not to continue its Consumer Electronics (CE) business. It was however clarified that this would not impact the company’s focus on its chips for mobile phones.

This comes closely on the heels of the revelation by LSI Corp. that it repurchased 5 million shares, worth $43 million, of its common stock in the past couple of days following its stock tumbling more than 12%; investors sold off the stock following the chipmaker's April 25 earnings report, in which LSI said its sales for the quarter ending in June would fall $100 million of Wall Street's expectations

While 60% of the revenue of the new combined company ((LSI Logic finalized its merger with Agere Systems in April and the new entity is called LSI Corp.) continues to come from its storage chips and systems business, does it mean an inclination of LSI Corp. towards the strengths of Agere Systems i.e. communications, networking and mobile phone industry?

While CE is generally considered to be a major revenue generator, it is not exactly a smooth sailing - decreasing market window, multiple features, growing design & packaging complexity, falling ASPs and convergence are some of the existing challenges

Singapore's 5M$ wafer fab training program funding

The Economic Development Board (EDB) has recently announced that it will invest over $5 million over the next three years into a program, Wafer Fabrication Specialist Manpower Program, designed to groom more wafer fabrication experts at local universities; aim is 300 new engineers to meet the chip industry demand.

The funds jointly contributed by the government and industry, would be used to provide monthly stipends of up to $710 to engineering undergraduates specializing in wafer fabrication in their final years of study at the National University of Singapore and Nanyang Technological University.

With more & diverse career options available to the students and the emerging of newer semiconductor/microelectronics hotbeds in the region, this program may help to address the manpower gap faced by the industry.

A bug.....

Read some interesting trivia in a book, “The Silicon Boys” by David A. Kaplan on origin of “bug” i.e. a computer bug....

The University of Pennsylvania’s ENIAC (Electronic Numerical Integrator and Computer) in 1946 was the first attempt at a large scale digital computer. It was a huge thing and had 18000 vacuum tubes. The warmth & light of ENIAC’s tubes presented a problem – moths liked them and would trigger short circuits. Hence “computer bug” meant a problem inside and “debugging” meant fixing it!

Convergence outcome unclear but opportunity rich

I read an interesting article on the recent iSuppli European Briefing series held in Hungary and reported by Drew Wilson in Electronic Business.

While iSupply sees consumers with 2 main devices: one handset for communications & information and the other one for entertainment with internet, gaming, music & video, Nokia forecasts the merging of all useful functions into one gadget. Its senior analyst also predicts the death of the stand alone camera.

Ideally users would gravitate towards a single device. However, categorizing “useful functions” is a formidable task. Consumers will weigh the pros & cons of the category contents. Ease of use, cost, weight, form factor, features available vs. used, services available & related logistics to use those features, product life time etc. are just some of the variables entering the picture. As a user, I would prefer a single device but not at the cost of sacrificing on ease of use of my “basic functions” requirement. e.g. my phone can have the latest add-on features but if the OS hangs or access time is long or I’ve to dig deep into my pockets to pay the service provider and with newer versions popping into the market before one even familiarizes with an older model- well that’s one road I’m not likely to tread on.

While I see one set of people converging to a single device, I see a not insignificant market (rather a bigger chunk) which would opt for 2 main devices. The low-mid end standalone digital cameras will become obsolete as the technology develops and costs come down. But that in no way signals the demise of high end standalone digital camera. People will still likely take the standalone camera for their holidays and serious clicking leaving the on-impulse shots and convenience pics to the converged portable device e.g. their mobile phone with camera.

The other interesting point highlighted was the change in biz model. The huge market comes along with myriad standards, IPs, tech know-how and more stake holders from varying & multiple sectors. The challenge will be to pave a seamless integration path. This will be mandatory given the life-cycle & competitive costs of consumer products

ESL tool targets algorithm for FPGA, ASIC devices

Synplicity rolled out its Synplify DSP ASIC Edition software at the Design Automation and Test Europe conference in France. Their earlier ESL synthesis tool was aimed at FPGA designs. With this new offering, they are targeting customers who use FPGA prototyping for their DSP based ASICs.

Another recent news has been that TSMC is broadening its IP portfolio giving worries to IP providers and speculation in the industry whether TSMC is moving towards ASIC like biz model.

Gives a new meaning to the phrase “ASIC demise”………

TSMC's IP moves stir up concern among providers

TSMC is broadening it’s portfolio of internally developed IPs and 3rd party IPs. It had started a program called IP-9000, later renamed to Active Accuracy Assurance Program, to qualify various IPs in its foundries. The objective was to expedite the design time with silicon proven 3rd party IPs.

With shorter design cycle time and with IPs becoming mandatory blocks in a design, the need for silicon proven IPs is not just desirable but also essential. Having a broad and quality IP portfolio is a big asset. If TSMC is getting into the ASIC like biz model, then indeed it is worrisome for the 3rd party IP vendors; especially the smaller ones who aspire to gain market share on the basis of their expertise in niche areas. The field gets all the more “unlevel”. But then it is a competitive world and TSMC would be leveraging on its resources and market reach.

A point to be noted is that, does this mean the resurrection of ASICs - often ranted about as dead ??

UMC joins CPF standard alliance

UMC is the latest one to join the Cadence camp. Earlier this month, Cadence and TSMC had announced the availability of 65nm libraries from TSMC supporting CPF (Common Power Format).

The market forces will decide who the winner is; but the poor user has to cope with this standards battle in the interim.

Medical field may push India's IC industry

TI’s CEO & President, Rich Templeton, mentioned the importance of medical equipment biz for India’s semiconductor industry during his visit to India.

Applications in the medical area, along with automotive applications hold prominence in the near future for the semiconductor industry in general, albeit a lot more in emerging markets like India and China. While consumer and telecom applications still remain strong contenders and are mainstream applications, the potential for these emerging segments is huge.

The shortened market window & pricing pressures for applications like entertainment/computing etc. falling under the generic consumer umbrella doesn’t give a leveling field to the smaller or niche players. This is where these yet to be fully tapped markets like medical and automotive hold the lure. Emerging market with strong potential which does not necessarily require the leading edge process ….. these can very well also pave the way for process choice in the soon to be set up foundries in India.

The dilemma of two languages in low power design

So, hopes of a single power format seem remote and it is increasingly likely that the industry will need to support both standards i.e. CPF as well as UPF. Well, now the market forces will decide the winner……

HSMC to chip in 4 bn$ for Indian fabs

I had reported in an earlier post “India outlines long awaited IC policy”, that the Indian govt.’s announcement of Special Incentives Package Scheme is likely to be followed by announcements by potential investors.

While SemIndia had already proposed investment in partnership with AMD, the latest one is from Hindustan Semiconductor Manufacturing Corporation (HSMC), a Silicon Valley-based semiconductor company. It has announced its plans to invest over $4 billion in chip foundries in India and has roped in Infineon as its technology partner; Infineon will license its 0.13u process techno and has said that it is open to considering an equity participation ‘subject to the final contract’.

According to a study by Frost and Sullivan, the semiconductor market in India is expected to grow from $3.25 billion in 2006 to $36 billion in 2015. The Indian govt. has announced Special Incentives Package Scheme, MoUs are being signed, what is to be seen now is the implementation of these plans and the coming up of the fabcities.

India's semiconductor policy - the ongoing debate

Read this article (Nadamuni says, in EE Times) ; Wanted to submit my comments there but looks like a perpetual error while submitting comments.....

2 issues which could be of concern to the fledgling Indian semiconductor market are: potential overcapacity situation and offering an attractive pricing strategy in face of strong competition from established regional foundries.

Investing with new equipment in light of the above and especially with the unavailability of incentives for such plants i.e. with second hand semiconductor equipment will make the potential investors wary.

However, having said that, if India were to offer the same set of incentives for second hand semicon equipment too, it’ll take a long time for it to catch up with cutting edge technology fabs as well as to address the design needs of the local design houses which have emerged from working on trailing edge technos to the leading edge ones.
Perhaps, a different set of incentives could work……???

UMC to open support office in India

UMC has announced that it plans to open a support office in Hyderabad, India. The main charter is to support India based customers. This is close on heels with TSMC’s setting up office in Bangalore, India.

Are ASICs dead?

There were some very interesting insights from the commentary on the panel discussion on the above topic.

People have been long talking about the demise of ASICs….and these are still around. A good starting point taken, hence, was the definition of ASICs itself. ASICs have undergone a transformation over the years and have evolved much from the traditional cell based ASICs.

Some interesting comments raised included:

- why have ASICs survived? Inspite of ridiculous prices, extremely unreliable and extremely unpredictable. Because they are needed. People talk about a decline in design starts…I think what we should be talking about is how many total transistors, total functionality and how much total revenue is being shipped. All of those numbers are increasing (Sherwani/OpenSilicon)
- Architecture is the key. More integration is not necessarily the right solution (Massabki/ChipX)
- How outsourcing and offshoring of basic R&D is affecting ASIC biz (Sherwani)

When we talk about ASICs declining, what are we referring to? Is it the number of design starts? And if so, which designs does this number include: cell based ASICs, embedded array, structured ASICs? Is it the total revenue?

Without a clear definition and specific measuring criteria, blanket statements do not make much sense.

Cisco, IBM team up on open standards communication platform

Cisco and IBM are planning to develop a platform based on open standards to allow unified communications and collaborations in their applications. IBM will offer a set of application programming interfaces (APIs) as a subset of its Lotus Sametime collaboration software and Cisco will offer communication APIs for accessing voice and video services.
Cisco and IBM also will roll out "specific client offerings" based on the new platform and a set of "plug-ins" to combine the collaboration and unified communications capabilities of both companies.

I had written about the adoption of a similar approach in the EDA industry (Why can’t we do it in EDA). Especially with DFM and other UDSM challenges (and not to mention the standards’ war!), it is to the advantage of the designer if he can get the best of all tools in a unified integrated design flow. Since no single vendor can handle this on its own, a collaborative approach looks to be the best bet.

Integrated DFM solutions still lacking

Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing noted in his presentation at the SPIE Advanced Lithography Conference last week that while there are some good point tools for DFM, integrated DFM solutions are still lacking.

As I noted in an earlier post, Why can’t we do it in EDA?, it is a huge task for a single vendor to handle even most of the important sources of variations through a single integrated flow. Integration of point tools requires standardization as well as agreement over interfaces and formats.

IBM’s Leon Stok had identified 4 eras in the EDA industry. For the 4th era i.e. design implementation platforms, he mentioned that we would need to define standards as APIs in order to allow tools to talk to each other.

The trend is moving more and more towards a hybrid approach

India outlines long awaited IC policy

After several hiccups, India has announced its IC policy.

Dubbed the Special Incentive Package Scheme, the initiative is focused on attracting investments for setting up semiconductor plants and other technology manufacturing industries. Semiconductor companies seeking incentives—which will be 20 percent of the capital expenditure during the first 10 years—will have to invest a minimum $550 million, according to the plan.

The salient points were announced Feb. 22 with details to be out in the coming two weeks in a document that spells out the specifics about the level of equity, the interest-free component and other financial details.

This announcement is most likely to be followed by announcements by potential investors. AMD has already announced a technology pact with SemIndia Inc. for a semiconductor manufacturing facility in Hyderabad.

At least two more semiconductor manufacturing facilities are expected to be announced in the next few weeks, according to Raj Khare, chairman, India Semiconductor Association.
Samsung, Freescale, Motorola, Intel, Infineon, STMicrorelectronics and Toshiba are among the possible investors in a Rs.20,394 crore ($4.5 billion) manufacturing facility being set up by the Hindustan Semiconductor Manufacturing Corp. (HSMC) which is expected to establish a fabrication complex that will include several foundries to be built by HSMC. The fabs will 200- and 300mm wafer lines.

It has to be seen if and how the various consortiums as well as companies like Intel etc. tread on this “red carpet” rolled out by the Indian govt. And having decided to tread, it has to be seen which technology direction will these new fabs take up (as noted in my earlier post, “Vision Summit explores strategies driving semicon industry growth”)

Blaze DFM merges with Aprio

So, the DFM consolidation has begun…..

While acquisitions of DFM companies by EDA vendors was already there, this is the first merger between 2 DFM companies. Blaze’s parametric DFM expertise complements Aprio’s lithography analysis skill-set. Together they can synergize on DFM analysis as well as optimization and address both manufacturing as well as the designer sets.

I had pointed out in an earlier post “Who will be left standing in DFM”, that in the consolidation phase, it will be a selected few who stand a chance to survive. Together, Blaze DFM-Aprio do come under this category.

Will this serve as the catalyst for further such mergers and pave way for “pure play DFM vendors” as opposed to EDA vendors selling DFM as a part of their “complete design flow portfolio” ??

NEC exits Structured ASIC market

Yet another company exits the Structured ASIC arena. After LSI Logic and then Synplicity, it’s now the turn of NEC. This is in line with a string of closures/layoffs and policy changes announced by Mr. Nakajima, NEC’s president.

NEC feels that Structured ASICs have not grown to a big biz yet and is risky to invest large resources in it. This is further aggravated when the company itself is not doing well overall.

Why is it that Structured ASICs hasn’t caught on? The general thinking when Structured ASICs evolved was that as long as there is the issue of high NREs and long design cycle time compounded by increasing risks involved with new designs/new techno/short market window etc., there will be a need to address the gap between FPGAs and Cell based ASICs. Structured ASICs definitely address this gap.

Could a possible reasoning be in the marketing strategy of Structured ASICs ??? As some one had pointed out a few years back……”Most of the companies that make structured ASIC products made their real money from cell-based ASIC lines. With FPGA companies eating into their profits from the bottom, they rolled out structured ASIC lines in retaliation. Their natural instinct, then, was to position these products directly against FPGAs. The problem with that positioning is that structured ASICs make a much more compelling solution when compared with cell-based products. Since most structured ASIC lines' lowest density is close to the highest density available in FPGA, there really isn't much overlap between single FPGAs and single structured ASICs. A structured ASIC is a good replacement for a two-or-more FPGA system, but the one-to-one replacement isn't often an option. Against cell-based designs, however, structured ASICs are stellar. They have much shorter design cycles, an order of magnitude lower NRE, much lower design tool costs, significantly less expertise required for success, and very competitive performance, density, power, and unit cost. The marketing mavens at these companies are understandably reluctant to launch an all-out assault on their own revenue generators, however, so they have put together campaigns that probably confused the customer more than they promoted this very compelling technology”

Grading of India's semicon industry

ISA-Ernst & Young, India’s recently released report presents a snapshot of India’s semicon industry.
Some of the salient points are:
Talent quality: Moderate (US rated very high)
Talent Availability & scalability: Very Well (4th amongst peers, US rated 3rd )
Technical education quality: Moderate (rated 5th, US rated very high)
Talent cost advantage: Very well (Best along with China, US rated lowest)
Peer countries selected for study: Canada, China, Czech Republic, India, Israel, Taiwan, the United Kingdom and the United States

Other than the more prevalent known aspects as cited above, the report underscored a few interesting and vital points:
- India’s need to conceptualize & build products and move up the value chain
- Relatively lower level of electronics manufacturing which adversely impacts the semicon market potential
- Need to increase IP registration

Statistical tool avoids overdesign with excessive margins

A new tool in the DFM arena –

Solido Design Automation has announced a tool for transistor level statistical design & verification. Unlike most of the DFM touted tools in the market, this one is to be used by designers prior to layout.

It promises 5 basic capabilities –
1. Statistical sampling that describes how processes can vary so that circuit simulators can estimate possible outputs.
2. Tradeoff analysis that lets users adjust specifications to impact yield
3. Statistical characterization, that shows the user how to improve the design to make it more robust to process variations.
4. Statistical circuit enhancement that automatically optimizes designs by sizing transistors.
5. Statistical visualization lets users explore and view the data.

Looks like a comprehensive set….

Post-silicon debugging worth a second look

With verification consuming up to 70% of design effort and debug up to 50% of that time (this means up to 35% of overall design time is spent understanding how a design works or why it doesn't!) - I share Richard Goering’s musing that it’s a wonder that EDA vendors have paid little attention to post-silicon debug.

Post-silicon validation being a confrontational sale may be a significant hurdle for selling wares in this space. However another not so insignificant fact is that post-silicon validation is done in 2-3 phases – first on standalone chip, then on the system and then the field trials. The latter two being heavily dependant on applications and the working environment pose too many variables in the debug process and it is not an easy task to implement all these in a tool. Nevertheless it is a fact that good solutions in this space will be a boon to the chip designer (not to say the S&M guys who keep their fingers crossed while awaiting reports of field tests and subsequently news on the 1st order…)

Vision Summit explores strategies driving semicon industry growth

A couple of contrasting views over the fab technology direction that India should follow was reported from the ISA Vision Summit 2007. While one view stated that it’ll be prudent for India to initially establish manufacturing capacities in older technologies and address those requirements which are not addressed by the more competitive larger multinational companies. Else it will fall prey to overcapacity problem.

A conflicting view presented some of the alternate views of addressing the overcapacity situation. In India’s case, it can be by focusing on technologies which are driven by applications of the products required by the local market i.e. applications are the fab techno drivers and not any predetermined process geometry.

Who will be left standing in DFM?

An interesting exchange of ideas reported in Electronics News recently.

DFM is the bridge between design and manufacturing. Most of the tools in the DFM arena are now towards the manufacturing side i.e. improving OPC while a selected few are focusing on the design part of the bridge. I agree with the viewpoint that in the consolidation phase, it will be these selected few who stand a chance to survive. Moving from binary rules based info to distribution information coming from manufacturing is not a smooth transition…..

TSMC sets up office in India

TSMC has announced the opening up of its office in Bangalore, India with the primary mission of supporting its existing customers with design activities in India. They see a huge increase in the number of advance technology designs coming from India.

What surprises me is their delay till date. With no major advance tech fab in the country, delays in fab investments/policies and spurt of fabless design companies, there had long been the potential of strengthening biz thru local presence.

Cadence deploys CPF

Cadence has deployed CPF (Common Power Format) into its existing tools. Rather than making it available as a special feature in tools that would have to be paid for separately, Cadence has made most of its existing tools CPF compliant.

While this makes it more convenient for the user on one hand, he expresses the design power intent/requirements just once and then the system/design flow takes care of the rest, it provides a potential blocking factor for user should the industry embrace an alternate power format (UPF or a third one).

However, Cadence has said, "Wherever the industry takes CPF and UPF, if the users want it, we'll do it. If you're a Cadence customer, as of now, the power standards thing is over. Go make chips. Whether it's CPF or UPF or some common thing in the future doesn't matter any more. We've got the software system that will build the chips, and we'll follow wherever the standard goes."

Let’s see what follows from the rival potential standard’s camp……

Intel and 45nm technology breakthrough

Intel is hogging the silicon limelight with it’s news on the technology breakthrough - usage of high-k and metal gate transistors for 45nm technology.

Scaling without losing out much on leakage is the driving advantage. The major advantage, though, is that with this technique, Intel will not have to significantly change its current production process. This is different from the alternative solution being disclosed by IBM and its partners. The latter involves SOI which is a more expensive production technique and they plan to later switch to immersion lithography. Another lead for Intel is that the production with this new technique starts mid this year whereas IBM plans production in end 2008.

Having said that, it still appears that while Intel has stolen the lead in announcing the breakthrough with earlier production planned (and that too across servers, desktops and laptop applications), IBM will have a long term advantage as its technology involves integration of the metal gates so that they are embedded in silicon as compared to Intel where they sit atop a proven silicon architecture – thus solving long range problems and more future transitions.

Freescale places R&D bet with IBM

Another salvo to Crolles2 Alliance. After NXP’s announcement on its exit from Crolles2 Alliance, comes the statement from Freescale that it is joining the IBM Alliance.

Apart from investing in leading edge chip R&D, some of the potential benefits for Freescale in this alliance are leveraging capacity at Chartered and possible wireless co-development efforts with Infineon. Freescale also expects to significantly accelerate its SOI roadmap with this IBM partnership.

This leaves STM as the lone original member of the Crolles2 alliance. A potential new partner will need to have deep pockets to fund expansion of the group’s 300mm fab as well as work on 45nm and beyond processes. This is apart from a good fit from the technology standpoint. TI is touted as one of the possible candidates. However with the latest announcement from TI to end leading edge digital logic process development at 45nm and rely on foundries is set to have important implications on this.

Low Power Specification Format War

Cadence’s primary EDA rivals felt that Power Forward Initiative introduced by Cadence in May ’06 wasn’t open and inclusive and joined another coalition – Accellera UPF effort in Sep. Si2’s Low Power Committee (LPC) was set up in Oct as an attempt to bridge the gap and address users’ requirement of having a single low power specification format.

Si2 first approved CPF 1.0 saying that its approval of CPF 1.0 does not constitute taking sides and that they have declared it as a “specification” and not a “standard”. This may be a conciliatory offer to Accellera which said that they are actively working with Si2 to converge UPF and CPF into a single standard. Then Si2 issued a RFT to complement the CPF and Cadence in its response has now provided them the source code of its CPF 1.0 parser; in the process opening the door to tool implementation that supports CPF ……. and hence giving another push to boost their format

NXP exits Crolles2 Alliance

In its new avatar, Philips Semiconductor, now NXP exits Crolles2 Alliance, a partnership formed in 2000 and renewed in 2002, and teams up with TSMC.

As we further scale the technologies and the fab and associated costs increase, alliances is no longer an option; it’s mandatory. Amongst the present big ones, the Chartered, IBM, Samsung, Infineon alliance seems to be the more promising one overall. IBM is also reportedly in talks with the other two Crolles2 partners, STM and Freescale, to join Crolles2 Alliance.

Freescale had been pushing to get IBM into the Alliance while STM was pushing for TSMC. NXP has an asset lite strategy (it plans to increase its outsourcing ratio to 40% by 2010, from its present 10-20%) and it seems logical for it to strengthen its cooperation with its long time foundry partner, TSMC.

Characterization tool for SSTA

A boost to SSTA…..Altos has introduced Variety, a SSTA library characterization tool. While there do exist similar tools in the market, Altos’ niche factor is that it supports multiple formats (unlike Cadence, Synopsys, IBM, Magma etc. which support only their proprietary formats). This is definitely an advantage as it gives flexibility to the user to switch across various flows/vendors.

Characterization speed and accuracy, the two most important aspects in library characterization, are something which Altos promises through this tool.

Apple unleashes iPhone

While launching iTV, Apple CEO, Steve Jobs mentioned, "Apple is in your den, in your living room, in your car, and in your pocket, I hope this gives you a little bit of an idea of where we're going."

Now a few months down the road, Apple has indeed added another gizmo for the pocket by introducing iPhone. Yet another player in the mobile phone/smart phone market. This time, however, as it is from iconic Apple, expectations are bound to be (“ahem”) a bit different – stylish, user friendly and features rich??

Waiting to see whether iPhone will have the same success as the iPod….
Apple’s shares have already registered a 6.7 % increase with the latest product launches – first Apple box/iTV and now iPhone.