Panelists ponder challenges at 45 nm

The volumes need to justify the high costs involved in 45 nm. Costs include the mask cost (with 2 M$ not being ruled out), design challenges, variability & yield issues to count a few. The consumer market is the major drive for cost reduction and high volumes. However, it needs to be kept in mind that the market windows in this segment are shrinking. To capitalize on these high volumes, chip vendors need to be nimble enough to get the 45 nm product out in time – a feat which is getting tougher as one scales down in the DSM zone.

As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.

Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.

No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.

Excessive guardbanding should not cut back the gains arising from the scaling to this technology.

As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..