Cisco turns to ZTE in China

While most other competitors foresee more growth in China, Cisco sees an edge in India and is investing heavily there. The things going for India include an unregulated economy, less competitive environment & a growing market . It’s worries in China include weaker IP protection laws and an edge to home grown local companies like Huawei, Harbor Networks etc. through loans and government support.

The Cisco-ZTE co-operation agreement will let Cisco take advantage of ZTE’s position in the local service provider market and it’s customer knowledge.

More on DFM....

I read this paper, “Yield challenges require new DFM approach” by P.T Patel in EE Times. It’s very well written and informative.

Yet another pointer to making the existing design tools (the focus in the article was on routing) more suitable for getting your design manufacturable.

Can someone explain DFM ?

Quite an interesting article in Electronic Engineering Times by Richard Goering.

Getting to basics ….

In commercial space, a designer designs a chip with the objective that it should not only function as per specs but also be manufactured in a commercially viable mode. This is implicit. Else shouldn’t we have heard about tools like Design for Silicon Success/DFSS or DFFTSS….??

Yes, we do have flows which aim for FTSS but not point tools. The point tools facilitate various design phases like simulation, synthesis, routing etc. but it’s a design flow which optimizes their usage to achieve objectives like intended functionality , high yield. In fact, all the existing design tools should have this “DFM” embedded in them by default.

Designers need not become manufacturing experts and the tools should be good enough to handle the yield issues in a transparent and automatic manner. But with the mandatory breaking of walls between design and manufacturing in the DSM zone, it does help for the designer to be aware of the potential manufacturing issues and take them into account while designing in order to avoid corrections at later stages.

Is Infineon going fabless ?

One of the potential solutions in addressing the challenges in manufacturing sub 90nm is in greater collaboration. How many of the existing top semiconductor companies can afford to be profitable while keeping their legs in both chip design as well as optimal yield DSM manufacturing ? One needs to focus upon ones’ strengths while leveraging with ones’ partners on others. Partnerships are extending; it’s a need & not just an option.

It makes me reflect on an article posted in Silicon Strategies on 12/27/2004, “15 predictions for IC, equipment biz in 2005 and beyond” which had a compilation of 15 predictions for the IC and chip-equipment industries in 2005 and beyond and listed some foundry marriages.

The sifting is being done……..

Unshackled IBM Microelectronics savors Game Box wins

Unshackled IBM Microelectronics savors Game Box wins - a very interesting article by Ed Sperling in a special report, Movers & Shakers 2005, in Electronic Business online.

Lining up 3 top gaming platforms, Sony PlayStation 3, Microsoft Xbox 360 and the follow on to the Nintendo GameCube as customers for it’s Cell Processor is a real volume play. In the absence of any real killer application, high volumes design wins do not come easy.

Steven Longoria, vice president of semiconductor technology platforms in IBM's Systems and Technology Group mentions that getting it’s technology consistent to avoid repetition of development steps is IBM’s top priority.

This is one area in the industry which usually takes a backseat amongst other priorities and is a major cause of ASIC design re spins. With the high mask costs, FTSS is getting more & more significant thus putting an ASIC vendor with a good track record of FTSS higher on the ASIC clients’ list. The shrinking market windows also do not leave much room for re spins.

Indian design activity on fast track, says iSuppli

Market research company, iSuppli Corp noted in a recent article posted in Electronic Engineering Times by Peter Clarke that India’s semiconductor design industry will nearly triple by 2010; it’s predicted to be 624M$ in ’05.

Investment in India needs to be for a long term strategic reason. Companies jumping into the bandwagon solely for cost reduction will most likely lose out. Some of the very factors driving the growth of the semiconductor industry here e.g. low cost design talent, strong education infrastructure and rapidly growing local market lead to challenges like high attrition rate. While money is a major factor for employee retention, career growth conducive work environment with interesting & innovative work on latest technology will help.

The other challenge of lack of trained designers is being addressed by the industry along with academia leading to several training start-ups which deliver mid & short term courses for fresh engineering graduates as well as working executives for VLSI careers.

Panelists ponder challenges at 45 nm

The volumes need to justify the high costs involved in 45 nm. Costs include the mask cost (with 2 M$ not being ruled out), design challenges, variability & yield issues to count a few. The consumer market is the major drive for cost reduction and high volumes. However, it needs to be kept in mind that the market windows in this segment are shrinking. To capitalize on these high volumes, chip vendors need to be nimble enough to get the 45 nm product out in time – a feat which is getting tougher as one scales down in the DSM zone.

As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.

Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.

No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.

Excessive guardbanding should not cut back the gains arising from the scaling to this technology.

As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..

Moore's Law

The microelectronics industry owes much to Moore’s Law – the number of transistors on a chip double every 2 years. It’s a principle which has been solid and consistent for the last 3 decades.

In an article posted by Bill Roberts in Electronic Business, Satoru Ito, CEO of Renesas Technology says. "Because of Moore's Law, the industry has had a common road map for technological innovation. This allows partnerships and planning for investment."

It’s an economic barometer with geometric scaling transforming to economic scaling.

Moore’s Law has led to partnership. For no single entity, no matter how deep it’s pockets are and how well entrenched it is with brain power, can work out on it’s own the complexities in the microelectronics ecosystem paved by this law.

It has led to specialization. Semiconductor equipment materials, foundries, EDA, Contract manufacturing, IPs, yield management processes – it has spawned them all. It has spurred entrepreneurial culture without which technology’s potential could not have been realized. And with specialization and innovation not recognizing any geographical boundaries, it has further led to globalization. Biz interests make you go where there is infrastructure, cost saving, brain power, innovation – strategy reason. Moore’s law has sustained because it’s driven by pure economics. Geometric scaling is a prelude to diminishing the cost.

And it has also led to the omnipresent question - after Moore's Law, what ???

India to take stake in fab project

It’s heartening to note Indian government’s proactive stance in putting India’s footprint on the hardware arena too. Several multinationals have a design/R&D setup in India. While most initially came for the comparatively cheap manpower, they’ve stayed put for the brain power and are now investing for innovation. Several local services and product companies too have sprung up. But what has been lacking is an efficient semiconductor manufacturing base i.e. fabs & testing entities. Developing and sustaining them is a formidable task as it’s an extremely capital (& commitment) intensive zone.

Taiwan’s ITRI is a good example to follow in guiding the technological and economic growth of the country. ITRI lists establishing new High tech industry, upgrading traditional industries, leading the drive for sustainable growth and developing highly skilled human resources under their industrial impact. It has played a vital role in turning this island state into a semiconductor hub housing world’s top two foundries and boasting of highly skilled designers.

IBM backs VCs, startups to pursue platform aims

IBMs’ VC Group’s strategy outlines a varying and rewarding approach to the functioning of a ventures capital arm of a large company. Deviating from the well trodden path of investing cash for ROI, it is emphasizing more on relationships, interests’ alignment and development of a mutually supported ecosystem.

As IBM Corp. VP & MD of it’s VC group, Claudia Fan Munce, stresses in an article in EE Times, the access IBM gains to companies in emerging technos and geographies is worth much more than the return on the cash itself. IBM’s involvement with VC firms and startups aids it in setting it’s technology agenda and pushing it through.

Especially in Asian countries where the right networking/connections building (or guanxi as is called in Chinese) is so important for biz growth, this strategy looks more effective than the relatively “cold” dollars vs return.

Consumer Era gives birth to "Gigafabs"

With consumer electronics joining PCs and internet based communications as a major semiconductor industry driver, fabs are getting into another league – Gigafabs. TSMC’s Mark Liu differentiates between the fabs on the basis of monthly wafers capacity – 80 to100K qualify as gigafabs while megafabs have a run rate of 50k wafers.

Consumer electronics market has a very short market window including a steep ramp up and leaves little room for redesigns. High price elasticity ranges encompass some real high priced niche products on one end and basic generic commodity tagged products on the other – and both categories can lead to massive volumes if the timing/placing-features-price combo target is hit.

Gigafabs help here because no vendor would like to be placed in a position where he has hit the market with the right product at the right time only to run out of fab capacity – a major biz opportunity loss. Also chips produced cheaper in the fabs (an advantage of gigafabs) can be sold cheaper. While gigafabs help to spread out the costs, not all players can join in due to the high costs involved.