Comments on “UMC’s Hu envisions a new model for foundry business” in Electronic Engineering Times by Ron Wilson
While it’s true that the leading foundries in this age must have the capabilities of an integrated device manufacturer, the transition from foundry to solutions provider is not an altogether new biz model nor is it an entirely different vision for foundry companies.
Quite a few years back, when foundries, especially in Taiwan, realized that low cost was no longer sufficient for their intended growth, they started focusing more on their IP portfolios. Design support also evolved into working on actual design issues and in some cases offering design services.
To cite a few……
TSMC offers IP portfolio, Design Centre Alliance, In house and 3rd party library services and Assembly & Testing services to some extent.
Chartered offers IP Access & Design Access.
Some are transitioning into this model with 3rd party collaboration while some try to develop it in-house. Foundries also hold an additional advantage in addressing DFM issues.
Wednesday, October 05, 2005
Saturday, October 01, 2005
ASIC makers piece together their options
Refering to "ASIC makers piece together their options" – Ron Wilson & Brian Fuller in EE Times
In an ideal world, the various entities i.e. Design company, foundry, EDA vendor, Packaging, Testing etc. will work together with the customer in a free information flow environment (albeit respecting each others IP rights). Bolstered by the information flow, they can provide collectively the customer with an optimal product (good design, good yield) whilst retaining their focus on their individual targets – and their bottom lines.
But, alas, it’s not the world we live in. And hence we see various strategies for surviving in this market - Fujitsu Microelectronics may be alleviating it’s new process risk costs by spreading it across it’s internal customers and LSI Logic by going fabless while sustaining itself on it’s excellent IP portfolio etc. – as cited in the article.
The partnership model between Chartered, IBM and Samsung will be interesting to watch - what with the potential of a customer being able to tape out with any of the 3 partners and then be able to select any of the 3 (not necessarily the same) as the foundry. How many ASIC semiconductor companies i.e. with both design & foundry capabilities, would be willing to go through the ASIC development only to see another company being chosen as the foundry ? ASICs are still taken up for their final revenues based on ASPs and not just the NREs. Or is this leading to supplementing of required know-how while possibly complementing on other skill-sets ??
In an ideal world, the various entities i.e. Design company, foundry, EDA vendor, Packaging, Testing etc. will work together with the customer in a free information flow environment (albeit respecting each others IP rights). Bolstered by the information flow, they can provide collectively the customer with an optimal product (good design, good yield) whilst retaining their focus on their individual targets – and their bottom lines.
But, alas, it’s not the world we live in. And hence we see various strategies for surviving in this market - Fujitsu Microelectronics may be alleviating it’s new process risk costs by spreading it across it’s internal customers and LSI Logic by going fabless while sustaining itself on it’s excellent IP portfolio etc. – as cited in the article.
The partnership model between Chartered, IBM and Samsung will be interesting to watch - what with the potential of a customer being able to tape out with any of the 3 partners and then be able to select any of the 3 (not necessarily the same) as the foundry. How many ASIC semiconductor companies i.e. with both design & foundry capabilities, would be willing to go through the ASIC development only to see another company being chosen as the foundry ? ASICs are still taken up for their final revenues based on ASPs and not just the NREs. Or is this leading to supplementing of required know-how while possibly complementing on other skill-sets ??
Monday, September 26, 2005
Freescale partners with Indian Design Houses
Comments on “Freescale partners with Indian Design Houses” by K.C Krishnadas in EE Times
This is indeed a strategy leading to multiple mutual benefits i.e. if implemented in the right spirit.
The right IP, the right technology, the optimal design flow, the right timing: neither of these factors can hold on their own in today’s volatile market. The customer wants a solution, not a set of leggo blocks left to him to assemble together.
Most of the design houses have some excellent design talent coupled with great technology, flow and ideas. But the present highly fragmented and transient market makes it very difficult for these design houses to even survive the initial few years before they hit the market and revenues start trickling in. The ruthless market conditions have led to the premature demise of many a promising design houses. With the multinationals tapping on these entities for domain know how and a basic solution using their IPs and the design houses leveraging on the multinationals’ clout (financial and market channels), it can be a win-win situation.
This is indeed a strategy leading to multiple mutual benefits i.e. if implemented in the right spirit.
The right IP, the right technology, the optimal design flow, the right timing: neither of these factors can hold on their own in today’s volatile market. The customer wants a solution, not a set of leggo blocks left to him to assemble together.
Most of the design houses have some excellent design talent coupled with great technology, flow and ideas. But the present highly fragmented and transient market makes it very difficult for these design houses to even survive the initial few years before they hit the market and revenues start trickling in. The ruthless market conditions have led to the premature demise of many a promising design houses. With the multinationals tapping on these entities for domain know how and a basic solution using their IPs and the design houses leveraging on the multinationals’ clout (financial and market channels), it can be a win-win situation.
Monday, September 19, 2005
Open-Silicon automates the flow
Refering to When infrastructure is essence: Open-Silicon automates the flow , an article posted in Electronic Engineering Times by Ron Wilson on Sep 16 2005
ASIC implementation is a complex procedure.
Automating it is more complex.
And adhering to the automated flow & achieving the intended results is an art in itself.
Every ASIC design team would have ventured into attempting to automate the complete process at least once in it’s life time. From my experience, it’s not the complexities involved (in the methodology or the automation), nor is it the lack of resources; but it is the good old discipline (or lack of it) that keeps one away from achieving the benefits of this automation. The biggest spoke in such an automation is the varied sets of designs, each with it’s unique baggage of complexities and requirements. Deviations are bound to occur if one needs each design to be optimized. So, it’s heartening to note that Open Silicon’s automated flow intends to include such creative detours.
It takes time (and restraint) to include all details; version control, detailed comments, personal tweaking, coding practices etc. I recollect the time when I had to put on hold all library releases by my team in order to include version control; it was not one of my favorite periods ! But yes, the subsequent gains more than supplemented for it.
Having developed, implemented as well as managed a gamut of automations across various ASIC implementations spanning various geographies, I adhere to the age old wisdom : A tool is as good as it’s implementation.
ASIC implementation is a complex procedure.
Automating it is more complex.
And adhering to the automated flow & achieving the intended results is an art in itself.
Every ASIC design team would have ventured into attempting to automate the complete process at least once in it’s life time. From my experience, it’s not the complexities involved (in the methodology or the automation), nor is it the lack of resources; but it is the good old discipline (or lack of it) that keeps one away from achieving the benefits of this automation. The biggest spoke in such an automation is the varied sets of designs, each with it’s unique baggage of complexities and requirements. Deviations are bound to occur if one needs each design to be optimized. So, it’s heartening to note that Open Silicon’s automated flow intends to include such creative detours.
It takes time (and restraint) to include all details; version control, detailed comments, personal tweaking, coding practices etc. I recollect the time when I had to put on hold all library releases by my team in order to include version control; it was not one of my favorite periods ! But yes, the subsequent gains more than supplemented for it.
Having developed, implemented as well as managed a gamut of automations across various ASIC implementations spanning various geographies, I adhere to the age old wisdom : A tool is as good as it’s implementation.
Friday, September 16, 2005
Taiwan as centre of IC world
Comments on “Seeing Taiwan as centre of IC world”, an interview of Nicky Lu by Mike Clendinin
IPs fill up the differentiating edge gap in a product leading to higher sales and thus higher revenues. But the broad definition of IP has also changed over the years. What was initially termed as the “winning” block in a chip has now become a generic part. So one needs to keep up innovating to come up with new IPs, new value-addition to the IC.
In the “manufacturing reigns supreme” years, Taiwan had the edge of having the wafer fab, assembly & testing plants as well as multiple design houses in the vicinity. Later when this along with the lower cost was no longer sufficient, foundries started focusing more on their IP portfolios and now on addressing the various issues arising in the design chain, in addition to the manufacturing issues. This has also been a triggered by the need of the “falling of the walls” between the design space and manufacturing space. Forced or not, this is good for the industry especially in the DSM zone.
Given the earlier edge of having in place the basic semiconductor ecosystem, Taiwan can be strongly poised if it can efficiently harness the synergy from it as an integral unit rather than as separate entities.
IPs fill up the differentiating edge gap in a product leading to higher sales and thus higher revenues. But the broad definition of IP has also changed over the years. What was initially termed as the “winning” block in a chip has now become a generic part. So one needs to keep up innovating to come up with new IPs, new value-addition to the IC.
In the “manufacturing reigns supreme” years, Taiwan had the edge of having the wafer fab, assembly & testing plants as well as multiple design houses in the vicinity. Later when this along with the lower cost was no longer sufficient, foundries started focusing more on their IP portfolios and now on addressing the various issues arising in the design chain, in addition to the manufacturing issues. This has also been a triggered by the need of the “falling of the walls” between the design space and manufacturing space. Forced or not, this is good for the industry especially in the DSM zone.
Given the earlier edge of having in place the basic semiconductor ecosystem, Taiwan can be strongly poised if it can efficiently harness the synergy from it as an integral unit rather than as separate entities.
Thursday, September 01, 2005
Leaky chips test designers' skills
Refering to Leaky chips test designers' skills by Mike Clendinin in www.eetasia.com
Yes, one can no longer rely upon deploying the power optimization techniques in the later part of the design. For that matter, it’s not sufficient to keep it restricted to any one design phase. It needs to be strategized and implemented right from algorithmic level, through architecture level and down to the placement & route phases. The higher the level, the more power savings one gets.
And there’s a constant balancing act between the various design constraints i.e. power, area and timing……..at least as of now.
Yes, one can no longer rely upon deploying the power optimization techniques in the later part of the design. For that matter, it’s not sufficient to keep it restricted to any one design phase. It needs to be strategized and implemented right from algorithmic level, through architecture level and down to the placement & route phases. The higher the level, the more power savings one gets.
And there’s a constant balancing act between the various design constraints i.e. power, area and timing……..at least as of now.
Monday, August 22, 2005
Are ESL and DFM false hopes ?
Refering to Are ESL and DFM false hopes? by Richard Goering in www.eetasia.com -
ESL and DFM are the two buzzwords in the DSM design space. With the spiraling costs involved, such techniques are getting into the mandatory zone. If we say that ESL is too domain and application specific, it’s just following another important trend in the market – that of structured ASICs/platform ASICs. You get master slices for various applications and these are further customized as per actual requirement. Is the industry, having moved from a “single EDA vendor toolset for a complete integrated design flow” to a “unified design flow integrated with various point tools from multiple EDA vendors” headed towards one with “point tools with a user defined interface for point customizations” ?
DFM surely requires a strong close link between the designer and the foundry but are the foundries ready for this ? The skyrocketing costs of setting up new fabs with the DSM processes led the foundries to partner together. Will the lure of acceptable yield and revenues henceforth get a similar result between IDMs and foundries ?
ESL and DFM are the two buzzwords in the DSM design space. With the spiraling costs involved, such techniques are getting into the mandatory zone. If we say that ESL is too domain and application specific, it’s just following another important trend in the market – that of structured ASICs/platform ASICs. You get master slices for various applications and these are further customized as per actual requirement. Is the industry, having moved from a “single EDA vendor toolset for a complete integrated design flow” to a “unified design flow integrated with various point tools from multiple EDA vendors” headed towards one with “point tools with a user defined interface for point customizations” ?
DFM surely requires a strong close link between the designer and the foundry but are the foundries ready for this ? The skyrocketing costs of setting up new fabs with the DSM processes led the foundries to partner together. Will the lure of acceptable yield and revenues henceforth get a similar result between IDMs and foundries ?
Wednesday, August 17, 2005
Advent of Program Management in ASIC implementation
ASICs started getting complex. Teams got globally dispersed. This was now no longer restricted to the foundries or the chip backend operations but also to the design team. Add to that a customer sitting in another location. To get a synergy across these islands of expertise for a FTSS moved Program Management role to a necessity. A necessity highlighted by the spiraling cost of design re-spins and exacerbated by the fragmented and transient market requirements.
From my experience, here are a few enablers for successful program implementation:
- Pro-active involvement right from the beginning i.e. from RFQ evaluation.
- Clear formulation of the specs mutually agreed and signed by both vendor and client. In this transient market, modifications are inevitable. However time spent in getting the basic set right is worthwhile.
- A well defined program schedule with clear allocation of resources and checklists
and it’s effective implementation. There are many software packages in the market; however keep in mind that a tool is as good as it’s implementation
- Effective communication
In my experience, lack of effective communication has been a major source of delays and issues cropping up in the program. Technical issues and logistic problems may be sorted out with a lesser impact. And it’s not just a language difference. Cultural and personality issues are not insignificant here. Effective documentation, a good rapport, increased presence, periodic meetings & regular updates, conference calls followed up by a written summary are a few enablers here.
- Anticipate and pre-empt issues and effective workarounds/solutions for problems
A good grasp of the complete ASIC supply chain provides an excellent leverage here. A good Program Manager can foresee the implications of decisions taken in a particular program phase, e.g. design on another phase e.g. packaging, on the ASIC program; a fact which may be lost on an engineer sitting in his island of expertise.
From my experience, here are a few enablers for successful program implementation:
- Pro-active involvement right from the beginning i.e. from RFQ evaluation.
- Clear formulation of the specs mutually agreed and signed by both vendor and client. In this transient market, modifications are inevitable. However time spent in getting the basic set right is worthwhile.
- A well defined program schedule with clear allocation of resources and checklists
and it’s effective implementation. There are many software packages in the market; however keep in mind that a tool is as good as it’s implementation
- Effective communication
In my experience, lack of effective communication has been a major source of delays and issues cropping up in the program. Technical issues and logistic problems may be sorted out with a lesser impact. And it’s not just a language difference. Cultural and personality issues are not insignificant here. Effective documentation, a good rapport, increased presence, periodic meetings & regular updates, conference calls followed up by a written summary are a few enablers here.
- Anticipate and pre-empt issues and effective workarounds/solutions for problems
A good grasp of the complete ASIC supply chain provides an excellent leverage here. A good Program Manager can foresee the implications of decisions taken in a particular program phase, e.g. design on another phase e.g. packaging, on the ASIC program; a fact which may be lost on an engineer sitting in his island of expertise.
Friday, July 29, 2005
PDA fad is over
Peter Clarke’s article PDA fad is over makes a compelling reading.
The appeal of the decreasing form factor in consumer gadgets made it’s advent not too long ago and was quickly embraced by the “young-on the move-possess-latest-gizmo” crowd. Along with came the expectation of packing of multiple features leading the industry to be perpetually kept on a delicate balancing act of features vs. size. And in features selection too, you have yet another formidable task. In the beginning, there were multiple gadget categories (you have a camera, a phone, an electronic diary etc.). But now you have a varying mix with blurred demarcations. The question that props up in the consumer’s mind is : do I go for a PDA phone or a phone PDA ?? A Blackberry is great for keeping me in sync with my email messages and to enforce my presence in this 24/365 flat world scenario, but how efficient is it to help me in calling and receiving telephone calls ?
And thus enters a plethora of gadgets, each with a dominant set of features catering to a specific market segment. It is difficult, if not impossible, to cater to all the transient and ever growing consumer requirements, into a handheld gadget with a long battery life and…. just to make life simpler “get the product out ASAP in market windows which are shrinking almost in line with the semiconductor process technology”! and I have not yet touched on pricing.
And that is where lies one of the major challenges : anticipating and gauging the consumer’s interests and preferences, getting the right mix (like Coke’s secret formula, but then even they were forced to innovate to sustain the consumers’ changing tastes!) and a continuous innovation (rather spin-offs from a basic model to be cost effective).
The appeal of the decreasing form factor in consumer gadgets made it’s advent not too long ago and was quickly embraced by the “young-on the move-possess-latest-gizmo” crowd. Along with came the expectation of packing of multiple features leading the industry to be perpetually kept on a delicate balancing act of features vs. size. And in features selection too, you have yet another formidable task. In the beginning, there were multiple gadget categories (you have a camera, a phone, an electronic diary etc.). But now you have a varying mix with blurred demarcations. The question that props up in the consumer’s mind is : do I go for a PDA phone or a phone PDA ?? A Blackberry is great for keeping me in sync with my email messages and to enforce my presence in this 24/365 flat world scenario, but how efficient is it to help me in calling and receiving telephone calls ?
And thus enters a plethora of gadgets, each with a dominant set of features catering to a specific market segment. It is difficult, if not impossible, to cater to all the transient and ever growing consumer requirements, into a handheld gadget with a long battery life and…. just to make life simpler “get the product out ASAP in market windows which are shrinking almost in line with the semiconductor process technology”! and I have not yet touched on pricing.
And that is where lies one of the major challenges : anticipating and gauging the consumer’s interests and preferences, getting the right mix (like Coke’s secret formula, but then even they were forced to innovate to sustain the consumers’ changing tastes!) and a continuous innovation (rather spin-offs from a basic model to be cost effective).
Wednesday, February 02, 2005
Welcome Me to Blogging World
This blog shall attempt to cover thoughts and ideas related to the VLSI Ecosystem
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