Low power IC design kit enables representative design

Cadence is slated to release its Low Power Methodology Kit in late June. The highlight of the kit is a wireless "representative design" implemented using multi-supply voltage and power shutoff methods. It comes with all the necessary command scripts and technology files to complete the design. The design has sample IP including a processor and bus fabric from ARM, Wi-Fi from Wipro, USB 2.0 from ChipIdea, 65nm low-power memories from Virage Logic and 65nm technology libraries from TSMC.

While till date, EDA vendors have been mostly dishing out different point tools to address the industry’s power concerns, a big challenge is to help designers utilize the appropriate low power techniques and tools effectively and seamlessly within their flow on a real design – and in a timely manner. They need to be aware of the trade-offs required and some balancing tips to make the exercise productive.

A representative design is a step forward in this direction. The objective may be to regain the lead in the format war, but if it helps the end user, it definitely signals well!

UMC joins CPF standard alliance

UMC is the latest one to join the Cadence camp. Earlier this month, Cadence and TSMC had announced the availability of 65nm libraries from TSMC supporting CPF (Common Power Format).

The market forces will decide who the winner is; but the poor user has to cope with this standards battle in the interim.

The dilemma of two languages in low power design

So, hopes of a single power format seem remote and it is increasingly likely that the industry will need to support both standards i.e. CPF as well as UPF. Well, now the market forces will decide the winner……

Cisco, IBM team up on open standards communication platform

Cisco and IBM are planning to develop a platform based on open standards to allow unified communications and collaborations in their applications. IBM will offer a set of application programming interfaces (APIs) as a subset of its Lotus Sametime collaboration software and Cisco will offer communication APIs for accessing voice and video services.
Cisco and IBM also will roll out "specific client offerings" based on the new platform and a set of "plug-ins" to combine the collaboration and unified communications capabilities of both companies.

I had written about the adoption of a similar approach in the EDA industry (Why can’t we do it in EDA). Especially with DFM and other UDSM challenges (and not to mention the standards’ war!), it is to the advantage of the designer if he can get the best of all tools in a unified integrated design flow. Since no single vendor can handle this on its own, a collaborative approach looks to be the best bet.

Integrated DFM solutions still lacking

Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing noted in his presentation at the SPIE Advanced Lithography Conference last week that while there are some good point tools for DFM, integrated DFM solutions are still lacking.

As I noted in an earlier post, Why can’t we do it in EDA?, it is a huge task for a single vendor to handle even most of the important sources of variations through a single integrated flow. Integration of point tools requires standardization as well as agreement over interfaces and formats.

IBM’s Leon Stok had identified 4 eras in the EDA industry. For the 4th era i.e. design implementation platforms, he mentioned that we would need to define standards as APIs in order to allow tools to talk to each other.

The trend is moving more and more towards a hybrid approach

Blaze DFM merges with Aprio

So, the DFM consolidation has begun…..

While acquisitions of DFM companies by EDA vendors was already there, this is the first merger between 2 DFM companies. Blaze’s parametric DFM expertise complements Aprio’s lithography analysis skill-set. Together they can synergize on DFM analysis as well as optimization and address both manufacturing as well as the designer sets.

I had pointed out in an earlier post “Who will be left standing in DFM”, that in the consolidation phase, it will be a selected few who stand a chance to survive. Together, Blaze DFM-Aprio do come under this category.

Will this serve as the catalyst for further such mergers and pave way for “pure play DFM vendors” as opposed to EDA vendors selling DFM as a part of their “complete design flow portfolio” ??

Statistical tool avoids overdesign with excessive margins

A new tool in the DFM arena –

Solido Design Automation has announced a tool for transistor level statistical design & verification. Unlike most of the DFM touted tools in the market, this one is to be used by designers prior to layout.

It promises 5 basic capabilities –
1. Statistical sampling that describes how processes can vary so that circuit simulators can estimate possible outputs.
2. Tradeoff analysis that lets users adjust specifications to impact yield
3. Statistical characterization, that shows the user how to improve the design to make it more robust to process variations.
4. Statistical circuit enhancement that automatically optimizes designs by sizing transistors.
5. Statistical visualization lets users explore and view the data.

Looks like a comprehensive set….

Post-silicon debugging worth a second look

With verification consuming up to 70% of design effort and debug up to 50% of that time (this means up to 35% of overall design time is spent understanding how a design works or why it doesn't!) - I share Richard Goering’s musing that it’s a wonder that EDA vendors have paid little attention to post-silicon debug.

Post-silicon validation being a confrontational sale may be a significant hurdle for selling wares in this space. However another not so insignificant fact is that post-silicon validation is done in 2-3 phases – first on standalone chip, then on the system and then the field trials. The latter two being heavily dependant on applications and the working environment pose too many variables in the debug process and it is not an easy task to implement all these in a tool. Nevertheless it is a fact that good solutions in this space will be a boon to the chip designer (not to say the S&M guys who keep their fingers crossed while awaiting reports of field tests and subsequently news on the 1st order…)

Who will be left standing in DFM?

An interesting exchange of ideas reported in Electronics News recently.

DFM is the bridge between design and manufacturing. Most of the tools in the DFM arena are now towards the manufacturing side i.e. improving OPC while a selected few are focusing on the design part of the bridge. I agree with the viewpoint that in the consolidation phase, it will be these selected few who stand a chance to survive. Moving from binary rules based info to distribution information coming from manufacturing is not a smooth transition…..

Cadence deploys CPF

Cadence has deployed CPF (Common Power Format) into its existing tools. Rather than making it available as a special feature in tools that would have to be paid for separately, Cadence has made most of its existing tools CPF compliant.

While this makes it more convenient for the user on one hand, he expresses the design power intent/requirements just once and then the system/design flow takes care of the rest, it provides a potential blocking factor for user should the industry embrace an alternate power format (UPF or a third one).

However, Cadence has said, "Wherever the industry takes CPF and UPF, if the users want it, we'll do it. If you're a Cadence customer, as of now, the power standards thing is over. Go make chips. Whether it's CPF or UPF or some common thing in the future doesn't matter any more. We've got the software system that will build the chips, and we'll follow wherever the standard goes."

Let’s see what follows from the rival potential standard’s camp……

Low Power Specification Format War

Cadence’s primary EDA rivals felt that Power Forward Initiative introduced by Cadence in May ’06 wasn’t open and inclusive and joined another coalition – Accellera UPF effort in Sep. Si2’s Low Power Committee (LPC) was set up in Oct as an attempt to bridge the gap and address users’ requirement of having a single low power specification format.

Si2 first approved CPF 1.0 saying that its approval of CPF 1.0 does not constitute taking sides and that they have declared it as a “specification” and not a “standard”. This may be a conciliatory offer to Accellera which said that they are actively working with Si2 to converge UPF and CPF into a single standard. Then Si2 issued a RFT to complement the CPF and Cadence in its response has now provided them the source code of its CPF 1.0 parser; in the process opening the door to tool implementation that supports CPF ……. and hence giving another push to boost their format

Characterization tool for SSTA

A boost to SSTA…..Altos has introduced Variety, a SSTA library characterization tool. While there do exist similar tools in the market, Altos’ niche factor is that it supports multiple formats (unlike Cadence, Synopsys, IBM, Magma etc. which support only their proprietary formats). This is definitely an advantage as it gives flexibility to the user to switch across various flows/vendors.

Characterization speed and accuracy, the two most important aspects in library characterization, are something which Altos promises through this tool.

Synthesis tool meets complex design rules

Yet another DFM tool in the market.

DFM Blaze announced a DFM tool, Blaze IF, to address topology variations caused due to CMP. It intelligently inserts dummy metal fill patterns into a design layout taking into account not only the design requirements like power and timing needs, but also the electrical issues like signal integrity and IR drop – which traditional approaches to metal fill do not accomplish.

This is in addition to the announcement of Blaze MO, announced earlier this year which provides guidance to OPC tool used in manufacturing through an annotation layer in the GDSII database. The tool optimizes the design by small tweaking of the gate lengths (within the process limits) for reducing leakage power and improving timings and provides this guidance to the OPC tool.

All these aim to bridge the gap between design and manufacturing. Instead of a blanket set of rules for the complete design, design specific and design objectives’ relevant optimizations are carried forward to the manufacturing. Making it an integral part of the flow before handoff to manufacturing is a step closer to address issues arising out of the open loop caused by changes made to the design after handoff – oblivious to the design issues which may be impacted.