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Common Platform Agreement extended to 32nm

IBM and its Common Platform agreement partners will extend their development relationship to 32nm too.

The group started with 2 partners – IBM and Chartered. This later included Infineon, Samsung, and now Freescale. In addition, with the collapse of Crolles Alliance, it can also draw more partners.

While collaboration is a necessity in these process nodes and the Common Platform Agreement has been doing quite well, there have been reports (which subsequently have been dismissed as rumours) that the foundry vendors in the alliance are struggling with compatibility issues - and this can get compounded with increasing number of members.

TSMC catches up with Intel on 45nm production

So, a foundry has closed the gap with an IDM!

In all likelihoods, TSMC will be in volume production for 45nm at the same time as Intel – in first half of 2008. As noted by David Manners in an an earlier post, “With all this third party expertise soaking up the industry’s value-add, where is there to go for the IDMs?”

TSMC makes IP but denies it is in IP business

Call it as seismic changes or consolidation, the chip manufacturing world is going through some upheaval. While on one end, quite a few IDMs are transitioning to a fab lite strategy (albeit in different flavours) - especially with the high costs & risks involved in sub 65nm, on the other end heavyweights like TSMC are spreading their reach into the IP arena too.

As I noted in an earlier post, TSMC is leveraging on its resources and market reach.It may start off as “strengthening the design collaboration for critical sub circuits” (who doesn’t want FTSS??) but the intensity of the move has been enough to spread ripples in the till now independent IP biz world. By doing so, TSMC may well be doing its share in mitigating some of the risks involved in DSM design and thus catalyzing more of these design starts; and subsequently fill up its high-end fabs.

STATS ChipPAC shareholders resist private equity buyout

In the recent spate of takeovers by the private equity world and at a time when the chip industry is undergoing consolidation, a blip has occurred – Temasek Holdings’ wholly owned subsidiary, Singapore Technologies Semiconductors Pte Ltd. (STSPL) has failed to complete its attempted buyout of test and assembly provider STATS ChipPAC Ltd. STSPL now has a majority stake of 83.1 percent in the company, falling short of the 90% required to make STATS ChipPAC completely private

Low power IC design kit enables representative design

Cadence is slated to release its Low Power Methodology Kit in late June. The highlight of the kit is a wireless "representative design" implemented using multi-supply voltage and power shutoff methods. It comes with all the necessary command scripts and technology files to complete the design. The design has sample IP including a processor and bus fabric from ARM, Wi-Fi from Wipro, USB 2.0 from ChipIdea, 65nm low-power memories from Virage Logic and 65nm technology libraries from TSMC.

While till date, EDA vendors have been mostly dishing out different point tools to address the industry’s power concerns, a big challenge is to help designers utilize the appropriate low power techniques and tools effectively and seamlessly within their flow on a real design – and in a timely manner. They need to be aware of the trade-offs required and some balancing tips to make the exercise productive.

A representative design is a step forward in this direction. The objective may be to regain the lead in the format war, but if it helps the end user, it definitely signals well!

Renesas seeks to keep its own process technology

Renesas seems to be bucking the trend of IDMs relying more and more on foundries for advanced process technology development.

Renesas believes in working (on its own or in collaboration) on advanced process development. With plans to increase sales in system-on-chip solutions and microcontrollers, it may make sense to keep the advanced process development in-house in order to have more control and direction for their major product offerings.

This, however, will not prevent it from outsourcing for volume production on advanced devices

TI takes two approaches to IC manufacturing

Mark LaPedus reports in his article in EETimes about TI’s approach towards IC manufacturing – while bolstering its in-house effort in analog production, TI is shifting more of its logic based work & process flow to foundries.

TI is adopting a 3 pronged approach based on its product categories - At the 65-nm node, TI has three foundry partners for its wireless chips: Chartered, TSMC and UMC. For wireless chips at 45 nm, TI will continue to use UMC and TSMC. For DSPs, TI develops the processes & makes its own 65nm DSP. However it will rope in TSMC too for the next node. TI has been manufacturing Sparc processors for Sun; a foundry, probably UMC, will take over production at 45nm.

Shifting the responsibility of digital processes to outside foundries, while focusing on analog processes for in-house manufacturing does seem to be the right direction, especially now when the production costs & risks are escalating. However, this is not an all together new approach. If I recollect well, STMicroelectronics had followed this approach along with TSMC. While the base/digital process was same across the two companies, STM developed its own spin-offs e.g. analog, high power, RF for and based on its market requirements.
The advantages are: risk sharing (in certain cases, offloading) in base process, retaining its niche in customized or spin-off processes and having the second source options when capacity is needed.

The article mentions that by using leading-edge foundries, fabless Qualcomm Inc. has been able to close the manufacturing gap with rival TI. I would say that it wasn’t just using leading edge foundries; it was close co-operation with multiple leading edge foundries coupled with the adoption of what it termed as Integrated Fabless Manufacturing Strategy (IFM) that helped Qualcomm. As I noted in my earlier post, "Fabless Qualcomm zooms to next node", (incidentally a comment on another article by the same author!) Qualcomm developed its own virtual manufacturing organization.

LSI Corp. may exit Consumer Electronics Biz

According to a news report, LSI Corp. is considering whether or not to continue its Consumer Electronics (CE) business. It was however clarified that this would not impact the company’s focus on its chips for mobile phones.

This comes closely on the heels of the revelation by LSI Corp. that it repurchased 5 million shares, worth $43 million, of its common stock in the past couple of days following its stock tumbling more than 12%; investors sold off the stock following the chipmaker's April 25 earnings report, in which LSI said its sales for the quarter ending in June would fall $100 million of Wall Street's expectations

While 60% of the revenue of the new combined company ((LSI Logic finalized its merger with Agere Systems in April and the new entity is called LSI Corp.) continues to come from its storage chips and systems business, does it mean an inclination of LSI Corp. towards the strengths of Agere Systems i.e. communications, networking and mobile phone industry?

While CE is generally considered to be a major revenue generator, it is not exactly a smooth sailing - decreasing market window, multiple features, growing design & packaging complexity, falling ASPs and convergence are some of the existing challenges

Singapore's 5M$ wafer fab training program funding

The Economic Development Board (EDB) has recently announced that it will invest over $5 million over the next three years into a program, Wafer Fabrication Specialist Manpower Program, designed to groom more wafer fabrication experts at local universities; aim is 300 new engineers to meet the chip industry demand.

The funds jointly contributed by the government and industry, would be used to provide monthly stipends of up to $710 to engineering undergraduates specializing in wafer fabrication in their final years of study at the National University of Singapore and Nanyang Technological University.

With more & diverse career options available to the students and the emerging of newer semiconductor/microelectronics hotbeds in the region, this program may help to address the manpower gap faced by the industry.

A bug.....

Read some interesting trivia in a book, “The Silicon Boys” by David A. Kaplan on origin of “bug” i.e. a computer bug....

The University of Pennsylvania’s ENIAC (Electronic Numerical Integrator and Computer) in 1946 was the first attempt at a large scale digital computer. It was a huge thing and had 18000 vacuum tubes. The warmth & light of ENIAC’s tubes presented a problem – moths liked them and would trigger short circuits. Hence “computer bug” meant a problem inside and “debugging” meant fixing it!

Convergence outcome unclear but opportunity rich

I read an interesting article on the recent iSuppli European Briefing series held in Hungary and reported by Drew Wilson in Electronic Business.

While iSupply sees consumers with 2 main devices: one handset for communications & information and the other one for entertainment with internet, gaming, music & video, Nokia forecasts the merging of all useful functions into one gadget. Its senior analyst also predicts the death of the stand alone camera.

Ideally users would gravitate towards a single device. However, categorizing “useful functions” is a formidable task. Consumers will weigh the pros & cons of the category contents. Ease of use, cost, weight, form factor, features available vs. used, services available & related logistics to use those features, product life time etc. are just some of the variables entering the picture. As a user, I would prefer a single device but not at the cost of sacrificing on ease of use of my “basic functions” requirement. e.g. my phone can have the latest add-on features but if the OS hangs or access time is long or I’ve to dig deep into my pockets to pay the service provider and with newer versions popping into the market before one even familiarizes with an older model- well that’s one road I’m not likely to tread on.

While I see one set of people converging to a single device, I see a not insignificant market (rather a bigger chunk) which would opt for 2 main devices. The low-mid end standalone digital cameras will become obsolete as the technology develops and costs come down. But that in no way signals the demise of high end standalone digital camera. People will still likely take the standalone camera for their holidays and serious clicking leaving the on-impulse shots and convenience pics to the converged portable device e.g. their mobile phone with camera.

The other interesting point highlighted was the change in biz model. The huge market comes along with myriad standards, IPs, tech know-how and more stake holders from varying & multiple sectors. The challenge will be to pave a seamless integration path. This will be mandatory given the life-cycle & competitive costs of consumer products

ESL tool targets algorithm for FPGA, ASIC devices

Synplicity rolled out its Synplify DSP ASIC Edition software at the Design Automation and Test Europe conference in France. Their earlier ESL synthesis tool was aimed at FPGA designs. With this new offering, they are targeting customers who use FPGA prototyping for their DSP based ASICs.

Another recent news has been that TSMC is broadening its IP portfolio giving worries to IP providers and speculation in the industry whether TSMC is moving towards ASIC like biz model.

Gives a new meaning to the phrase “ASIC demise”………

TSMC's IP moves stir up concern among providers

TSMC is broadening it’s portfolio of internally developed IPs and 3rd party IPs. It had started a program called IP-9000, later renamed to Active Accuracy Assurance Program, to qualify various IPs in its foundries. The objective was to expedite the design time with silicon proven 3rd party IPs.

With shorter design cycle time and with IPs becoming mandatory blocks in a design, the need for silicon proven IPs is not just desirable but also essential. Having a broad and quality IP portfolio is a big asset. If TSMC is getting into the ASIC like biz model, then indeed it is worrisome for the 3rd party IP vendors; especially the smaller ones who aspire to gain market share on the basis of their expertise in niche areas. The field gets all the more “unlevel”. But then it is a competitive world and TSMC would be leveraging on its resources and market reach.

A point to be noted is that, does this mean the resurrection of ASICs - often ranted about as dead ??

UMC joins CPF standard alliance

UMC is the latest one to join the Cadence camp. Earlier this month, Cadence and TSMC had announced the availability of 65nm libraries from TSMC supporting CPF (Common Power Format).

The market forces will decide who the winner is; but the poor user has to cope with this standards battle in the interim.

Medical field may push India's IC industry

TI’s CEO & President, Rich Templeton, mentioned the importance of medical equipment biz for India’s semiconductor industry during his visit to India.

Applications in the medical area, along with automotive applications hold prominence in the near future for the semiconductor industry in general, albeit a lot more in emerging markets like India and China. While consumer and telecom applications still remain strong contenders and are mainstream applications, the potential for these emerging segments is huge.

The shortened market window & pricing pressures for applications like entertainment/computing etc. falling under the generic consumer umbrella doesn’t give a leveling field to the smaller or niche players. This is where these yet to be fully tapped markets like medical and automotive hold the lure. Emerging market with strong potential which does not necessarily require the leading edge process ….. these can very well also pave the way for process choice in the soon to be set up foundries in India.

The dilemma of two languages in low power design

So, hopes of a single power format seem remote and it is increasingly likely that the industry will need to support both standards i.e. CPF as well as UPF. Well, now the market forces will decide the winner……

HSMC to chip in 4 bn$ for Indian fabs

I had reported in an earlier post “India outlines long awaited IC policy”, that the Indian govt.’s announcement of Special Incentives Package Scheme is likely to be followed by announcements by potential investors.

While SemIndia had already proposed investment in partnership with AMD, the latest one is from Hindustan Semiconductor Manufacturing Corporation (HSMC), a Silicon Valley-based semiconductor company. It has announced its plans to invest over $4 billion in chip foundries in India and has roped in Infineon as its technology partner; Infineon will license its 0.13u process techno and has said that it is open to considering an equity participation ‘subject to the final contract’.

According to a study by Frost and Sullivan, the semiconductor market in India is expected to grow from $3.25 billion in 2006 to $36 billion in 2015. The Indian govt. has announced Special Incentives Package Scheme, MoUs are being signed, what is to be seen now is the implementation of these plans and the coming up of the fabcities.

India's semiconductor policy - the ongoing debate

Read this article (Nadamuni says, in EE Times) ; Wanted to submit my comments there but looks like a perpetual error while submitting comments.....

2 issues which could be of concern to the fledgling Indian semiconductor market are: potential overcapacity situation and offering an attractive pricing strategy in face of strong competition from established regional foundries.

Investing with new equipment in light of the above and especially with the unavailability of incentives for such plants i.e. with second hand semiconductor equipment will make the potential investors wary.

However, having said that, if India were to offer the same set of incentives for second hand semicon equipment too, it’ll take a long time for it to catch up with cutting edge technology fabs as well as to address the design needs of the local design houses which have emerged from working on trailing edge technos to the leading edge ones.
Perhaps, a different set of incentives could work……???

UMC to open support office in India

UMC has announced that it plans to open a support office in Hyderabad, India. The main charter is to support India based customers. This is close on heels with TSMC’s setting up office in Bangalore, India.

Are ASICs dead?

There were some very interesting insights from the commentary on the panel discussion on the above topic.

People have been long talking about the demise of ASICs….and these are still around. A good starting point taken, hence, was the definition of ASICs itself. ASICs have undergone a transformation over the years and have evolved much from the traditional cell based ASICs.

Some interesting comments raised included:

- why have ASICs survived? Inspite of ridiculous prices, extremely unreliable and extremely unpredictable. Because they are needed. People talk about a decline in design starts…I think what we should be talking about is how many total transistors, total functionality and how much total revenue is being shipped. All of those numbers are increasing (Sherwani/OpenSilicon)
- Architecture is the key. More integration is not necessarily the right solution (Massabki/ChipX)
- How outsourcing and offshoring of basic R&D is affecting ASIC biz (Sherwani)

When we talk about ASICs declining, what are we referring to? Is it the number of design starts? And if so, which designs does this number include: cell based ASICs, embedded array, structured ASICs? Is it the total revenue?

Without a clear definition and specific measuring criteria, blanket statements do not make much sense.

Cisco, IBM team up on open standards communication platform

Cisco and IBM are planning to develop a platform based on open standards to allow unified communications and collaborations in their applications. IBM will offer a set of application programming interfaces (APIs) as a subset of its Lotus Sametime collaboration software and Cisco will offer communication APIs for accessing voice and video services.
Cisco and IBM also will roll out "specific client offerings" based on the new platform and a set of "plug-ins" to combine the collaboration and unified communications capabilities of both companies.

I had written about the adoption of a similar approach in the EDA industry (Why can’t we do it in EDA). Especially with DFM and other UDSM challenges (and not to mention the standards’ war!), it is to the advantage of the designer if he can get the best of all tools in a unified integrated design flow. Since no single vendor can handle this on its own, a collaborative approach looks to be the best bet.

Integrated DFM solutions still lacking

Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing noted in his presentation at the SPIE Advanced Lithography Conference last week that while there are some good point tools for DFM, integrated DFM solutions are still lacking.

As I noted in an earlier post, Why can’t we do it in EDA?, it is a huge task for a single vendor to handle even most of the important sources of variations through a single integrated flow. Integration of point tools requires standardization as well as agreement over interfaces and formats.

IBM’s Leon Stok had identified 4 eras in the EDA industry. For the 4th era i.e. design implementation platforms, he mentioned that we would need to define standards as APIs in order to allow tools to talk to each other.

The trend is moving more and more towards a hybrid approach

India outlines long awaited IC policy

After several hiccups, India has announced its IC policy.

Dubbed the Special Incentive Package Scheme, the initiative is focused on attracting investments for setting up semiconductor plants and other technology manufacturing industries. Semiconductor companies seeking incentives—which will be 20 percent of the capital expenditure during the first 10 years—will have to invest a minimum $550 million, according to the plan.

The salient points were announced Feb. 22 with details to be out in the coming two weeks in a document that spells out the specifics about the level of equity, the interest-free component and other financial details.

This announcement is most likely to be followed by announcements by potential investors. AMD has already announced a technology pact with SemIndia Inc. for a semiconductor manufacturing facility in Hyderabad.

At least two more semiconductor manufacturing facilities are expected to be announced in the next few weeks, according to Raj Khare, chairman, India Semiconductor Association.
Samsung, Freescale, Motorola, Intel, Infineon, STMicrorelectronics and Toshiba are among the possible investors in a Rs.20,394 crore ($4.5 billion) manufacturing facility being set up by the Hindustan Semiconductor Manufacturing Corp. (HSMC) which is expected to establish a fabrication complex that will include several foundries to be built by HSMC. The fabs will 200- and 300mm wafer lines.

It has to be seen if and how the various consortiums as well as companies like Intel etc. tread on this “red carpet” rolled out by the Indian govt. And having decided to tread, it has to be seen which technology direction will these new fabs take up (as noted in my earlier post, “Vision Summit explores strategies driving semicon industry growth”)

Blaze DFM merges with Aprio

So, the DFM consolidation has begun…..

While acquisitions of DFM companies by EDA vendors was already there, this is the first merger between 2 DFM companies. Blaze’s parametric DFM expertise complements Aprio’s lithography analysis skill-set. Together they can synergize on DFM analysis as well as optimization and address both manufacturing as well as the designer sets.

I had pointed out in an earlier post “Who will be left standing in DFM”, that in the consolidation phase, it will be a selected few who stand a chance to survive. Together, Blaze DFM-Aprio do come under this category.

Will this serve as the catalyst for further such mergers and pave way for “pure play DFM vendors” as opposed to EDA vendors selling DFM as a part of their “complete design flow portfolio” ??

NEC exits Structured ASIC market

Yet another company exits the Structured ASIC arena. After LSI Logic and then Synplicity, it’s now the turn of NEC. This is in line with a string of closures/layoffs and policy changes announced by Mr. Nakajima, NEC’s president.

NEC feels that Structured ASICs have not grown to a big biz yet and is risky to invest large resources in it. This is further aggravated when the company itself is not doing well overall.

Why is it that Structured ASICs hasn’t caught on? The general thinking when Structured ASICs evolved was that as long as there is the issue of high NREs and long design cycle time compounded by increasing risks involved with new designs/new techno/short market window etc., there will be a need to address the gap between FPGAs and Cell based ASICs. Structured ASICs definitely address this gap.

Could a possible reasoning be in the marketing strategy of Structured ASICs ??? As some one had pointed out a few years back……”Most of the companies that make structured ASIC products made their real money from cell-based ASIC lines. With FPGA companies eating into their profits from the bottom, they rolled out structured ASIC lines in retaliation. Their natural instinct, then, was to position these products directly against FPGAs. The problem with that positioning is that structured ASICs make a much more compelling solution when compared with cell-based products. Since most structured ASIC lines' lowest density is close to the highest density available in FPGA, there really isn't much overlap between single FPGAs and single structured ASICs. A structured ASIC is a good replacement for a two-or-more FPGA system, but the one-to-one replacement isn't often an option. Against cell-based designs, however, structured ASICs are stellar. They have much shorter design cycles, an order of magnitude lower NRE, much lower design tool costs, significantly less expertise required for success, and very competitive performance, density, power, and unit cost. The marketing mavens at these companies are understandably reluctant to launch an all-out assault on their own revenue generators, however, so they have put together campaigns that probably confused the customer more than they promoted this very compelling technology”

Grading of India's semicon industry

ISA-Ernst & Young, India’s recently released report presents a snapshot of India’s semicon industry.
Some of the salient points are:
Talent quality: Moderate (US rated very high)
Talent Availability & scalability: Very Well (4th amongst peers, US rated 3rd )
Technical education quality: Moderate (rated 5th, US rated very high)
Talent cost advantage: Very well (Best along with China, US rated lowest)
Peer countries selected for study: Canada, China, Czech Republic, India, Israel, Taiwan, the United Kingdom and the United States

Other than the more prevalent known aspects as cited above, the report underscored a few interesting and vital points:
- India’s need to conceptualize & build products and move up the value chain
- Relatively lower level of electronics manufacturing which adversely impacts the semicon market potential
- Need to increase IP registration

Statistical tool avoids overdesign with excessive margins

A new tool in the DFM arena –

Solido Design Automation has announced a tool for transistor level statistical design & verification. Unlike most of the DFM touted tools in the market, this one is to be used by designers prior to layout.

It promises 5 basic capabilities –
1. Statistical sampling that describes how processes can vary so that circuit simulators can estimate possible outputs.
2. Tradeoff analysis that lets users adjust specifications to impact yield
3. Statistical characterization, that shows the user how to improve the design to make it more robust to process variations.
4. Statistical circuit enhancement that automatically optimizes designs by sizing transistors.
5. Statistical visualization lets users explore and view the data.

Looks like a comprehensive set….

Post-silicon debugging worth a second look

With verification consuming up to 70% of design effort and debug up to 50% of that time (this means up to 35% of overall design time is spent understanding how a design works or why it doesn't!) - I share Richard Goering’s musing that it’s a wonder that EDA vendors have paid little attention to post-silicon debug.

Post-silicon validation being a confrontational sale may be a significant hurdle for selling wares in this space. However another not so insignificant fact is that post-silicon validation is done in 2-3 phases – first on standalone chip, then on the system and then the field trials. The latter two being heavily dependant on applications and the working environment pose too many variables in the debug process and it is not an easy task to implement all these in a tool. Nevertheless it is a fact that good solutions in this space will be a boon to the chip designer (not to say the S&M guys who keep their fingers crossed while awaiting reports of field tests and subsequently news on the 1st order…)

Vision Summit explores strategies driving semicon industry growth

A couple of contrasting views over the fab technology direction that India should follow was reported from the ISA Vision Summit 2007. While one view stated that it’ll be prudent for India to initially establish manufacturing capacities in older technologies and address those requirements which are not addressed by the more competitive larger multinational companies. Else it will fall prey to overcapacity problem.

A conflicting view presented some of the alternate views of addressing the overcapacity situation. In India’s case, it can be by focusing on technologies which are driven by applications of the products required by the local market i.e. applications are the fab techno drivers and not any predetermined process geometry.

Who will be left standing in DFM?

An interesting exchange of ideas reported in Electronics News recently.

DFM is the bridge between design and manufacturing. Most of the tools in the DFM arena are now towards the manufacturing side i.e. improving OPC while a selected few are focusing on the design part of the bridge. I agree with the viewpoint that in the consolidation phase, it will be these selected few who stand a chance to survive. Moving from binary rules based info to distribution information coming from manufacturing is not a smooth transition…..

TSMC sets up office in India

TSMC has announced the opening up of its office in Bangalore, India with the primary mission of supporting its existing customers with design activities in India. They see a huge increase in the number of advance technology designs coming from India.

What surprises me is their delay till date. With no major advance tech fab in the country, delays in fab investments/policies and spurt of fabless design companies, there had long been the potential of strengthening biz thru local presence.

Cadence deploys CPF

Cadence has deployed CPF (Common Power Format) into its existing tools. Rather than making it available as a special feature in tools that would have to be paid for separately, Cadence has made most of its existing tools CPF compliant.

While this makes it more convenient for the user on one hand, he expresses the design power intent/requirements just once and then the system/design flow takes care of the rest, it provides a potential blocking factor for user should the industry embrace an alternate power format (UPF or a third one).

However, Cadence has said, "Wherever the industry takes CPF and UPF, if the users want it, we'll do it. If you're a Cadence customer, as of now, the power standards thing is over. Go make chips. Whether it's CPF or UPF or some common thing in the future doesn't matter any more. We've got the software system that will build the chips, and we'll follow wherever the standard goes."

Let’s see what follows from the rival potential standard’s camp……

Intel and 45nm technology breakthrough

Intel is hogging the silicon limelight with it’s news on the technology breakthrough - usage of high-k and metal gate transistors for 45nm technology.

Scaling without losing out much on leakage is the driving advantage. The major advantage, though, is that with this technique, Intel will not have to significantly change its current production process. This is different from the alternative solution being disclosed by IBM and its partners. The latter involves SOI which is a more expensive production technique and they plan to later switch to immersion lithography. Another lead for Intel is that the production with this new technique starts mid this year whereas IBM plans production in end 2008.

Having said that, it still appears that while Intel has stolen the lead in announcing the breakthrough with earlier production planned (and that too across servers, desktops and laptop applications), IBM will have a long term advantage as its technology involves integration of the metal gates so that they are embedded in silicon as compared to Intel where they sit atop a proven silicon architecture – thus solving long range problems and more future transitions.

Freescale places R&D bet with IBM

Another salvo to Crolles2 Alliance. After NXP’s announcement on its exit from Crolles2 Alliance, comes the statement from Freescale that it is joining the IBM Alliance.

Apart from investing in leading edge chip R&D, some of the potential benefits for Freescale in this alliance are leveraging capacity at Chartered and possible wireless co-development efforts with Infineon. Freescale also expects to significantly accelerate its SOI roadmap with this IBM partnership.

This leaves STM as the lone original member of the Crolles2 alliance. A potential new partner will need to have deep pockets to fund expansion of the group’s 300mm fab as well as work on 45nm and beyond processes. This is apart from a good fit from the technology standpoint. TI is touted as one of the possible candidates. However with the latest announcement from TI to end leading edge digital logic process development at 45nm and rely on foundries is set to have important implications on this.

Low Power Specification Format War

Cadence’s primary EDA rivals felt that Power Forward Initiative introduced by Cadence in May ’06 wasn’t open and inclusive and joined another coalition – Accellera UPF effort in Sep. Si2’s Low Power Committee (LPC) was set up in Oct as an attempt to bridge the gap and address users’ requirement of having a single low power specification format.

Si2 first approved CPF 1.0 saying that its approval of CPF 1.0 does not constitute taking sides and that they have declared it as a “specification” and not a “standard”. This may be a conciliatory offer to Accellera which said that they are actively working with Si2 to converge UPF and CPF into a single standard. Then Si2 issued a RFT to complement the CPF and Cadence in its response has now provided them the source code of its CPF 1.0 parser; in the process opening the door to tool implementation that supports CPF ……. and hence giving another push to boost their format

NXP exits Crolles2 Alliance

In its new avatar, Philips Semiconductor, now NXP exits Crolles2 Alliance, a partnership formed in 2000 and renewed in 2002, and teams up with TSMC.

As we further scale the technologies and the fab and associated costs increase, alliances is no longer an option; it’s mandatory. Amongst the present big ones, the Chartered, IBM, Samsung, Infineon alliance seems to be the more promising one overall. IBM is also reportedly in talks with the other two Crolles2 partners, STM and Freescale, to join Crolles2 Alliance.

Freescale had been pushing to get IBM into the Alliance while STM was pushing for TSMC. NXP has an asset lite strategy (it plans to increase its outsourcing ratio to 40% by 2010, from its present 10-20%) and it seems logical for it to strengthen its cooperation with its long time foundry partner, TSMC.

Characterization tool for SSTA

A boost to SSTA…..Altos has introduced Variety, a SSTA library characterization tool. While there do exist similar tools in the market, Altos’ niche factor is that it supports multiple formats (unlike Cadence, Synopsys, IBM, Magma etc. which support only their proprietary formats). This is definitely an advantage as it gives flexibility to the user to switch across various flows/vendors.

Characterization speed and accuracy, the two most important aspects in library characterization, are something which Altos promises through this tool.

Apple unleashes iPhone

While launching iTV, Apple CEO, Steve Jobs mentioned, "Apple is in your den, in your living room, in your car, and in your pocket, I hope this gives you a little bit of an idea of where we're going."

Now a few months down the road, Apple has indeed added another gizmo for the pocket by introducing iPhone. Yet another player in the mobile phone/smart phone market. This time, however, as it is from iconic Apple, expectations are bound to be (“ahem”) a bit different – stylish, user friendly and features rich??

Waiting to see whether iPhone will have the same success as the iPod….
Apple’s shares have already registered a 6.7 % increase with the latest product launches – first Apple box/iTV and now iPhone.

Private equity chips away at semiconductor industry

A highly interesting article in Electronic Business by Tam Harbert.
Private equity firms target cash rich semiconductor entities, leverage on its cash flow to borrow more funds and then restructure, improve the company’s bottom line and then sell it or take it public; providing returns of 30-40%. Tam lists the reasons behind recent LBOs in the semiconductor space – industry being driven by the less cyclic consumer market, transition to fab-lite/fabless models and a better control over inventory.

The question which arises is that why hasn’t the chip industry taken the necessary steps to consolidate and leave that task to the private equity guys? iSupply’s Derek Lidow cites portfolio management as the reason. While chip companies, usually run by engineers structure the portfolio on technology, private equity folks tend to manage groups of products on market segments and geographical regions; rather than technology criterion. They acquire and merge companies that have similar product portfolios.

While on mergers and acquisitions, Mentor Graphics’ CEO, Wally Rhines mentioned in a recent article that the role of acquisitions in EDA industry is set to change. As the acquisitions in the past few years have failed to garner commensurate market capitalization, he opines that companies will either pay less for acquisitions or stop making them.

No major fab investments for India in 2007 - Gartner says

Gartner predicts that there will not be any major fab investments for India in 2007. There indeed is a lot of buzz for India in the design space. It has led to major collaborations as well as investments. Global contract manufacturers have entered with an eye on the huge local market potential. While a few consortia have plans, some of which have started on their first stages, it will take some time before any further significant investment is done towards setting up fabs and moving India to a design plus manufacturing hub.

Synthesis tool meets complex design rules

Yet another DFM tool in the market.

DFM Blaze announced a DFM tool, Blaze IF, to address topology variations caused due to CMP. It intelligently inserts dummy metal fill patterns into a design layout taking into account not only the design requirements like power and timing needs, but also the electrical issues like signal integrity and IR drop – which traditional approaches to metal fill do not accomplish.

This is in addition to the announcement of Blaze MO, announced earlier this year which provides guidance to OPC tool used in manufacturing through an annotation layer in the GDSII database. The tool optimizes the design by small tweaking of the gate lengths (within the process limits) for reducing leakage power and improving timings and provides this guidance to the OPC tool.

All these aim to bridge the gap between design and manufacturing. Instead of a blanket set of rules for the complete design, design specific and design objectives’ relevant optimizations are carried forward to the manufacturing. Making it an integral part of the flow before handoff to manufacturing is a step closer to address issues arising out of the open loop caused by changes made to the design after handoff – oblivious to the design issues which may be impacted.

Cisco announces updates on its 1.1 B$ investments in India

In October 2005, John Chambers, Chairman and CEO Cisco Systems had announced a 1.1 B$ investment in India. In his recent visit to India last week, he re-iterated Cisco’s commitment while outlining the importance of India in Cisco’s global growth strategy.

Cisco’s key investments in India include a new R&D campus in Bangalore, increasing by threefold its local workforce, launching a manufacturing pilot facility for local market and allocating funds for venture capital investments in high growth and nascent companies based in India. Investments are expected in companies involved in broadband content and digital media.

All these are in line with John’s vision of the network becoming the platform for all forms of communication and ICT – also the topic of his interesting talk in Singapore last Friday.

Fabless Qualcomm zooms to next node

Qualcomm, with its IFM (Integrated Fabless Manufacturing) strategy is quietly but steadily decreasing the gap between itself and IDMs in new process adoption time. The world’s largest fabless design company is leading the way in how the fabless design community needs to overcome the DSM hurdles of the widening gaps between IC design and manufacturing flows.

While not exactly striving to be process experts, Qualcomm has formed a virtual manufacturing organization including its VLSI Technology organization and DFX unit which has helped it to understand, appreciate and thus resolve a host of complex and costly issues. The results, closing of the technology gap with the IDMs, are the proof.
They are cautious enough, though, as to not necessarily be the first ones to ship out a new product on a new technology node.

With Paul Jacobs’ strategy of making people understand that Qualcomm is a wireless technology company and not just a CDMA company, it needs all the efforts and results to zoom to the next node in a competitive manner.

Platform innovation will drive EDA

An interesting take on the EDA industry evolution and look into the trend by Leon Stok, director of EDA for IBM's Systems and Technology Group in a keynote address at the International Conference on Computer Aided Design (ICCAD).

Stok identified three previous innovation eras in the EDA industry — those of invention, implementation, and integration. The fourth era, he said, is the one we're about to enter and is centered on design implementation "platforms”. To make platform innovation happen, Stok said, we will need to define standards as APIs, not ASCII formats. This will allow tools to talk to each other, instead of producing data that another tool can barely read, he noted.

With APIs, smaller companies with innovative potential solutions for the UDSM technology challenges will have a more level playing field. Each can plug in their solutions and then let the market forces decide. It will also pave the way for the bigger players as they too can focus on the overall user flow with a market decided mix of their own in-house tools or point tools from other companies.

Designers give CAD research gurus an earful

The organizers of ICCAD (International Conference on Computer Aided Design) decided to do something different and added a designer’s perspective track this year.

"Our goal is to bridge the gap between practitioners and research," said ICCAD general chair Soha Hassoun, an associate professor of electrical engineering and computer science at Tufts University (Medford, Mass.), in opening remarks at the conference. "We would like them [designers] to tell you [researchers] what critical issues should drive CAD research in the next few years."

Now, I would term this as going back to basics. The users tell their requirements to the researchers which in turn guides the researchers towards the right direction in terms of practical benefits and usage of their efforts – optimal Lab to Fab transition.

Another tenet emphasized was by STMicroelectronics’ Pascal Urard: "We need academia and the EDA community to think at the flow level, not only at the tool level”.

It is apt to remind the EDA community that they should enable the end user with his final flow and not only the point tools. It’s true that tools provide the differentiating edge amongst the EDA vendors and users should have the flexibility of picking up the ones which best suit his flow.

However, to justify the “Automation” in “EDA”, it pays to facilitate the flow.

Taiwan’s design houses continue to attract buyouts

Atheros recently picked up Attansic Technology, a designer of Ethernet chips in Taiwan for its Gigabit Ethernet technology for 802.11n market. Attansic is a subsidiary of Asustek. Craig Barratt, CEO of Atheros said, “there has really been tremendous growth in companies in Taiwan doing pretty impressive R&D, creative engineering and product development.”

Moving to India – India needs to include IPs and technology know-how into their growing expertise portfolio. As I mentioned in an earlier post, product know-how is essential for the differentiating factor. With its relatively better copyright rules as compared to China for example, if the Indian companies can supplement their design skills and embedded software expertise with the product & technology know-how, they can raise the stakes higher.

There are some examples like Wipro, Tejas Networks etc. but it’ll be good to see this list grow.

India struggles to fill talent void

From what had earlier started as point engagements or doing auxillary services, semiconductor design companies in India are now working on not only the leading edge technologies (which they were still doing in the past as point engagements) but also end to end projects. In doing so, the Indian design engineers have been able to broaden their skill set as compared to quite a few of their international counterparts.

When you don’t have the so called luxury to specialize in certain niches areas and are thrust with the responsibility of doing multiple design tasks in order to get a design out, well, one learns and that too fast! A positive go-getter attitude coupled with a survival instinct honed by the competitive Indian environment (which starts right from kindergarten) also does help.

The early 90’s saw design companies in India getting supplementary work albeit some in leading edge technology. Of course, cost was the major reason. Once they instilled some confidence, it morphed into a bigger part of the design cycle. They started getting not only more designs but the opportunity and the responsibility to execute a design end to end and also complex designs. However technology innovations have still not figured within their purview.

Attrition: While this rate is high and experienced engineers switch jobs, money is not always the major deciding factor. Generically speaking, fresh graduates/ engineers with a couple of years experience rate the work quality and the company branding more than money. Mid range experience engineers value work quality, responsibilities and money. Professionals who return to India after working abroad are looking for challenging opportunities. I am not saying that money is not significant but rather that if the employee retention logic is through money alone, well, mate, you are throwing the wrong carrot…Indians have always had an entrepreneurial spirit (I attribute it to the urge to remove the shackles, something linked with our political history as well as the present political scenario).

Design ecosystem: While some may say that the absence of fabs is not a hindrance to the design scene in India, the fact remains that SoCs of today are not just built on design flow, IPs and library know how. One needs to have the product know how too – and this can become a major differentiating factor. And of course, trying out a new design concept in one country, fabricating in another and waiting for it to come back in order to do the tests, not to mention the red tape which may be involved, is something which one can do without. One of the reasons why Taiwan grew to a semiconductor hub is that it had design, fabrication, packaging and testing right there. So, while presently it may not sound so much of a missing link, it will gain importance if India is to take up China.

The above article was preceded, by just a couple of days, by another article appearing in Electronic business cited India’s niche: semiconductor design services. So if the talents void increases, India risks losing the niche.

Low cost phones soar in China

With technology advances, more & more features are being incorporated in the mobile phone. And the existing features are being further refined e.g. increasing video and audio quality and PDA functions thrown in. While this entices the young generation, executives as well as techno geeks across various generations and the upward swinging classes, there still remains two main chunks of a country’s population waiting to be tapped - the rural or economically backward set and the other is the senior citizens club – and both exist in all countries.

China and India with the world’s largest and second largest populations of course provide the maximum growth potential. The difference is in the 2 categories. While the rural/economically backward class will opt for a no frill mobile as their first set of mobiles or as an entry point in climbing up the economic ladder, the senior citizens will opt for it for the sheer reason of convenience and ease to handle. A small mobile bundled with the latest technology for camera, PDA functions, audio etc. is not of much use to them especially if they have to pound the miniature keys – not an easy task with age taking its toll on their movements and eye-sight. What they need is a simple robust instrument able to do the basic functions and perhaps with a little bit of audio, camera and games thrown in – at an affordable cost – remember they have retired. And the size should be small enough to be held conveniently in their pockets or hung around their necks but not so small so as to make them lose it.

Both sets require low cost phones and this is where single chip solutions hold an edge. And as pointed out in the article, chipmakers lacking single chip solutions will face increasing pressure to compete with those that have them.

This makes for an observation here – why are the mobile companies not targeting the older generations especially in the developed countries like Japan and some European countries where the ratio of senior citizens to youth is quite high…..???

Why can't we do it in EDA?

This was the questioned posed by Chairman of Orb Networks and former CEO of Cadence, Joe Costello in his DAC 2006 keynote speech.

The “it” referred to here is the mix and match of new plug-ins (internal and external), bundling things on top of others’ offerings and selling directly to customers.

With the increasing complexity of technological challenges compounded by rising market pressures, it does indeed benefit both the big EDA companies as well as the small start-ups with niche solutions to collaborate. However, opening the tools and making them pluggable is not without its major share of teething issues. While standards do take a long time to be formulated and then adopted, they’ll still be required to an extent for “universal plug-ins”.

One scenario is where EDA companies have the basic engines for the standard design activities. To these, smaller niche companies provide their plug-ins for value-addition and tackling of issues related to leading edge designs. With a uniform standard, these companies can go with their plug-ins to various EDA companies. In its absence however, each EDA company will need to work closely with these smaller companies and sell the complete “bundle with options” to the user.

A point to be noted here is that it’ll be naïve to assume that the present basic engines are implemented in a modular fashion where a plug-in can be used in a quasi seamless fashion. Then comes the question: if addressing of the leading edge issues is done in a modular fashion by the smaller companies who are free to sell their wares to the other big EDA companies, what is in it for the big EDA companies? What will be their competitive edge? But on the flip side, if the major EDA companies persist in attempting to do everything on their own, given the complexities and constraints, it’ll not result in much growth for the EDA industry.

Interestingly, there are signs of the industry moving in this direction. For DFM, with TSMC sharing their process information with the EDA companies to integrate into their design flow is one example. This can be treated as a “plug-in”.

Let’s take an example here: Synopsys recently came out with 3 tools in the DFM space - LCC (lithography compliance checking), CMP (chemical-mechanical polish) checking, and CAA (critical-area analysis). As per the press note, LCC inspects GDS-II files using a rapid-computation model of the lithography process, calibrated with foundry data. This scan predicts the actual shapes the mask features will produce, across the focus window of the lithography step. It then examines these features against a rule set to detect pinch-off, end-shortening, bridge, and other faults that could occur with a reasonable probability.

The normal output of the device is a color-coded die map: green for areas that pass, yellow for areas of concern, and red for trouble spots. Design teams that are knowingly pushing the litho rules can look under this graphic presentation at a numerical database that will give them actual predictions of critical dimensions.

Designers can then invoke an auto-correction tool, which is based on extensive, process-dependent heuristics, to deal automatically with the majority of the problems—adding space between lines, moving edges or corners, and other such reasonable measures.

Now reconsider the situation with a small EDA company working on the basic LCC part. It takes inputs from the lithography process model provided to it by the big EDA vendor (I don’t think the big foundries will be that comfortable in working closely with the smaller companies in handling their process data!). The GDSII is also provided as an input from the big EDA vendor’s tool(s). Finally the auto correction tool can be provided by either.

I cite this example because while these three new tools do attempt to handle the first order problems, they do not even begin to cover all the important sources of variation in 90-nm and finer geometries. TSMC cites more than 2000 independent sources of potential trouble.

I see a hybrid approach in the near future………

Should IP adopt a service biz model?

As pointed out in the article, most designers treat IP as a product. However, this product rarely comes with a guarantee; which is not that surprising. It’ll be almost suicidal given the argument that IPs are not plug in objects. Not only the IP’s functionality but also its interface and integration with the other components in the system determine whether the chip will work or not. And a standalone guarantee for an IP does not hold much credence.

A close working relationship between IP supplier and user has always been deemed vital for the successful IP usage and integration; hence to formalize it and bundle things under the “service” umbrella will not be that major a leap of faith.

China Syndrome Cooling ?

China Syndrome cooling, an article by Ed Sperling in Reed Electronics points out the possible waning of the “Invest in the Booming China Market” wave by electronics companies. Possible reasons cited by them for hedging their bets in other regions and in other countries include:

- China’s emphasis on allowing other cities besides Shanghai and Beijing to partake in the economic revolution is making it far more difficult for companies to manage logistics between their manufacturing sites inside of China;

- Rapidly rising labor costs are forcing some companies to consider comparable wage scales in places such as Vietnam, Malaysia and Eastern Europe;

- China’s ineffective policing of intellectual property theft has made many companies reluctant to move design operations there;

- Continued U.S. government regulations about what technology can be shipped into China or developed there has kept the lid on many companies’ plans;

- Manufacturers are looking to hedge their bets with backup strategies in case of a natural disaster or political issues that can affect regions.

Well, it makes economic and political sense for China’s emphasis to let its cities other than Shanghai and Beijing to invite investments so that they can have an inclusive growth – something vital for both the economic and political stability of a country else the economic disparity thus created would mitigate the growth achieved otherwise. To help the electronics companies, infrastructure improvement in these other cities could help.

Ineffective policing of IPs is indeed an important deterrent. However a few recent events are providing some progress. Hong Kong Science and Technology Parks Corporation (HKSTP) recently inaugurated the Intellectual Property Servicing Centre (IPSC) at the Hong Kong Science Park. Based within the Hong Kong Integrated Circuits Design Centre at the Park, it offers IP licensing, IP hardening, IP integration and IP verification services. Most notably, IPSC is run by HKSTP and will make use of Hong Kong law for any legal dispute over intellectual property. A key vehicle for this will be the Hong Kong International Arbitration Centre which is based in the SAR.

Under the “7+1” IC Design Centre framework signed with the High-Technology Research & Development Centre of the PRC’s Ministry of Science & Technology, HKSTP jointly collaborated with Harbin Institute of Technology, Hefei University of Science and Technology, Zhejiang University and the Hong Kong University of Science and Technology in July 2005 to extend the SIP trading platform throughout Greater China. The collaboration is to develop a due diligence platform in legal and technical terms for SIP certification and authentication purposes.

In October 2005, HKSTP also formed alliance with the China’s Ministry of Information Industry Software and Integrated Circuit Promotion Centre (CSIP) for the Mainland China IC design industry. The alliance is to promote the cooperation and development of Mainland China’s IC enterprises under the guidance and supervision of the administrative bodies, to jointly facilitate the outreach and popularization of SIP in SoC design services, as well as to standardize the SIP design, SIP standard promotion and SIP protection mechanism.

DFM again

TSMC had recently unveiled its 65nm DFM compliance design support ecosystem by coming out with its DFM Data kit compiled with DFM Unified Format (DUF). DUF has been developed by TSMC to align DFM tools. This kit would help to put the fabless designers on an equal footing with the IDMs. The format, though, models only random and systematic defects with parametric defects being planned for a future release.

Now yet another tool has hit the “in news” DFM space.

Blaze DFM Inc recently rolled out its solution Blaze MO. It is marketed as targeting to improve the parametric yield through a better control over leakage, timing and variability.
It has an electrical focus in contrast with other DFM tools which have a geometric focus (focusing on wire spreading, lithography simulation and critical area analysis)

The heat is on…….

Thermal Analysis

Thermal analysis is gaining momentum. While these analysis tools were there in the past especially with analog and mixed signal devices, they’ve lately gained prominence with sub 90nm digital designs too.

Thermal analysis tools track thermal gradients across the die. Uneven shifting of the threshold voltage, timing violations (clock timings are especially sensitive to delay variations caused by thermal gradients), leakage, electromigration, reliability are some of the thermal problems.

While some vendors are coming out with standalone thermal analysis tools e.g Gradient, some like Magma have thermal analysis in built into their power analysis tool as they believe that since power and temperature are interlinked, a user should not be shuttling between 2 separate analysis tools. As package plays a vital role in thermal analysis, some are getting package considerations also into the product.

Along with these tools, it’s the thermal management chips which are riding along the wave. According to Databeans, thermal management ICs could reach just under 2B$ in 5 years. The main growth segments cited are the ones using FPGAs and ASICs.

IC Design Houses survey by EE Times Asia (Taiwan, China)

A snapshot analysis from IC Design Houses Survey 2006 (China and Taiwan) report done by EE Times

A. Revenues
a. 2005 revenues (expected)
Average 5.4 M$ in China, 9.2 M$ in Taiwan
China
15 M$ and above–19 %,1-2.9 M$ - 19%,less than 250 K$ and 3-6.9M-17%
Broadly uniformly distributed
Taiwan
15 M$ and above – 37%, less than 250 K$ - 16%, 7-10.9 M$ and
11 – 14.9 M$ - 11%
Taiwan has extremes; 15M$ category followed by < 250k$ and the gap is expected to further widen in 2006.
b. 2006 revenues (forecasted)
China
15 M$ and above – 28% (a big jump from ’05)
Taiwan
15 M$ and above – 53% (a big jump with a marginal increase in the lower categories)
Basically, there is a broad and uniform representation by design houses in China for all categories – small to big. This is a reflection of several design houses appearing on China’s microelectronics landscape in the last few years. Taiwan, on the other hand, being more mature in this area has most of its design houses represented in the 15M$ category and then several smaller ones.

B. Applications
- Taiwan is predominantly desktop and Laptop computers followed by
handhelds and other consumer electronics.
- China has a more even spread across handhelds/PDAs, wireless consumers,
Cellular Wireless equipment & other telecom.
- Cellular/Wireless is more than LAN/WAN equipment in China; it’s the
reverse in Taiwan.
- China also has a higher percentage in Automotives which is a growing market
there.

C. Main difficulties when contracting foundries
China: Cycle time (54%) and cost (49%)
Taiwan: Cost (68%) and cycle time (45%)
Taiwan’s main application being Computing and Consumer Electronics which is a highly cost competitive market reflects this.

D. Design
a. Types
China
ASICs (66%), SoC (59%), Standard IC (29%), ASSP (8%) PLD/FPGA (17%)
Taiwan
ASICs (61%), SoC (53%), Standard IC (28%), ASSP (19%), PLD/FPGA (7%)

- Analog/Mixed signal designs to decrease in China while there is a
slight increase in Taiwan.
- China & Taiwan – Percentage of Digital ASICs as well as DSPs to
decrease, SoC will be more or less constant.
- Taiwan has more ASSPs, an indicator of the Consumer Electronics market
with consumer focused system designs that can be rapidly configured.
- Fewer newer designs are expected in 2006 but as revenues are
expected to increase, this may indicate more revenue/design in ’06
as compared from ‘05

b. Technology/Process
Average of 10 (Taiwan) and 8 (China) design projects in ’05 with
Digital design (Taiwan/China)
0.13um (11%/ 14%), 0.18um (48%/46%), 0.25u (11%/12%), 0.35u (15%/16%), 0.5-1.5u (15%/12%)
Analog design (Taiwan/China)
0.13um (2%/10%), 0.18um (32%/24%), 0.25u (11%/15%), 0.35u (22%/16%), 0.5-1.5u (24%/25%)

- 0.18um is the most frequently used technology in both countries.
- China has more designs in 0.13um both in analog and digital as compared
to Taiwan.
- Digital designs have more or less jumped from 0.35um to 0.18um with not
many in 0.25um. Analog/Mixed Signal designs are mostly in 0.5u and
above and in 0.18um

c. Gate Count in ASIC designs
Taiwan: 3 major blocks – Less than 50K, 100k to 299k and 1 to 2.49M
gates
China: More evenly spread. Bigger blocks are – 50k-99K, 500k to 999k,
1 to 2.49M gates

d. Challenges (Taiwan/China)
i. Reduction of design cycle time (60% / 60%)
Cycle time also figured highest for China under difficulties with foundries i.e. China’s biggest challenge is cycle time for both foundries as well as design cycle time while Taiwan has cost of foundries and design cycle time
ii. Reduction of design cost (51% / 46%)
iii. IP availability (23% / 23%)
iv. IP verification (18% / 16%)
v. DFT (5%/11%)
DFT figures higher in China. Can be attributed to higher gate complexity designs and types of designs (major applications - telecom equipment).
vi. Power Management (19% / 11%)
Power Management figures high in Taiwan after IP verification. This relates to the fact that Taiwan does a large chunk of designs for Consumer Electronics where power management is a major concern
vii. DFM (4%/ 1 %)
DFM figures higher in Taiwan. This may be attributed to the fact that the world’s top 2 foundries are from Taiwan. However, DFM is gaining momentum in sub micron technologies. So China with more designs moving to 0.13um as compared to Taiwan should have an equal if not higher figure for DFM under design challenges
viii. Design Iteration (5%/ 2%)
ix. Timing closure (5% / 2%)


E. Regional perspectives
IC design houses offer mostly Full system design followed by IP services. IP services is slightly higher in Taiwan w.r.t China (IP protection in China is a major concern and this reflected in the IP services numbers)

Turbulent times ahead, Gartner says

Gartner during it's mid year update outlined 5 megatrends facing the industry - continued integration due to Moore’s Law, increasing cost and scale of manufacturing facilities, the role the consumer markets will have going forward, service providers of various kinds, and a set of new and potentially disruptive technologies.

One more major trend that I perceive, is increasing collaboration. Whether it is OEMs collaborating with service providers or EDA companies/Design houses with foundries, this collaboration will increase. This is especially true for deep sub micron technologies.

Fewer chip designs will also re-enforce EDA companies to rethink their strategies and biz models. They will need to address solutions. As pointed out by Robert Hum/Mentor Graphics, “it is time for a change”. For verification, for example, realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. An open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

Technology innovations will continue, in fact grow faster. There will also be increase in the number of startups with each one of them trying to address some niche area in the market and trying to tap it in the mode they think best. However as pointed out by Gartner, the question is how many will survive the transitions.

Another outcome of fewer chip makers in the market due to increase in manufacturing scale will be the diminishing of manufacturing differentiation.

The market has moved more from standalone products to solutions. And solutions go hand in hand with service thus getting the service providers into a more prominent role. Service providers are nearer to the end customer and know their requirements which will also propel them towards a product defining role.

The growing power of the consumer market and keeping in mind its demands, will lead to more reconfigurable devices. The challenge, however, will be keeping the costs down as reconfigurability does not come with optimized silicon usage.

It's time for a change

Yes, indeed the methodology should be done by people who know it best i.e. design engineers. EDA companies should step in to facilitate this and not formulate them. We should not have situations where the design engineer needs to grapple with firstly the design & process complexities and secondly with trying to fit the design tool into his design methodology. With the increasing complexities associated with sub micron designs, there is a need for more and more collaboration. The tasks are too mammoth and interlinked for any single entity to manage on their own. Realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. Indeed an open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

Intellectual Capital

Yes, it indeed is true that the real assets of a company are it’s intellectual capital. Not being tangible in the conventional manner, this is not analysed to the extent it merits.

Increasing your market share without upsetting your profit margin ; and all this while not letting your intellectual capital diminish is indeed a juggling act. While globalization pushes companies to compete internationally against lower paying work forces, it also throws open the option of getting work done not only cost effectively but also Qualitatively.

We start with a lean organization with the core people – the identified and nurtured intellectual capital. Identify all the work/activities which can be outsourced. Give it to smaller companies which focus on that specific activity. Tap on the freelancers specializing in niche areas. We do see this in the present scenario too e.g. design houses, foundries, testing, distributors etc. However, the synergy here needs to be channeled and optimized. With global work forces, anyhow geographical barriers are falling. It’s pay per usage. The core employees formulate the strategies, give directions for the company’s growth and manage this knowledge bank of smaller companies and free lance professionals.

There are quite a few challenges to this approach but I do not think they are unmanageable. The biggest one would be IP protection. But then, that hasn’t deterred much the design activities or technology development/transfer to places like China. The recent panel on IP in China moderated by the president of SIA and as reported in Electronics News by Suzanne Deffree (dt. 3/3/2006) cites - China has the intellectual capability and the numbers. Barriers are not going to work. We have to try to safely enable them.

Virtual versus Vertical

Both ASIC and COT designs need the designer to fix the foundry at the onset. This is because the library and the design rules needed for both are supplied by the target foundry. COT, however, does have the flexibility for changing the foundry at a later stage provided the process is compatible across multiple foundries – however it still needs some verification to avoid problems on silicon. Multiple sources especially where one needs backups and also an advantage for price negotiations have been in the picture.

DFM does change a lot of value propositions. COT’s have been less costly not just because foundries compete on price but also because the extra service of design implementation in an ASIC comes with it’s own price tag. With DFM, the boundary between design and manufacturing is getting blurred and hence not many will opt for the traditional COT approach. Foundries will (and are) moving up in the design value chain.

With DFM, there is an increased need for foundries to share process information so that it’s taken into account during the design phase. Foundries collaborating with EDA vendors for this result into tools handling the yield issues while making it as transparent to the designer as possible. Design flows were devised and verified with specific tools (from single or multiple EDA vendors/sources) to tackle various design issues and facilitate FTSS. Now the verification of these flows includes another variable – foundry. i.e. a designer will need to know which foundry’s data has been used to verify the design flow before he starts using it.

Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty. There will be an economical need for them to see their foundries operate at capacity. For this, they will need to facilitate new designs in these technos; and hence they will be compelled to either share more information/collaborate or do every thing on it’s own i.e. a one stop shop.

TSMC executive sees more IP from foundry

To sell wafers, one needs tapeouts. Successful tapeouts require libraries and IPs validated on the target technology. And as technology advances, customers are more and more wary of getting their designs taped out with libraries and IPs not fully validated on silicon. So where does this lead a foundry with a ready advanced process but waiting for library & IP vendors to provide their wares on this new techno so that it can get customers’ designs in ?

Well, it provides libraries and IPs - either on it’s own or with partnerships. TSMC’s Europe Technical Director, Douglas Pattullo said in the IP/SoC conference in Grenoble on 7th Dec – TSMC is a provider not just of libraries but of complex IPs as well. He mentions that they are doing it to support their wafer manufacturing biz and not to get a new revenue stream.

It was once the same with EDA vendors. Quite a few of them started providing an IP portfolio – yes, to support their EDA biz. After all, customers are more comfortable with 3rd party IPs proven to be working in a specific design flow. But then as the process world started getting interleaved with the design world & the design space became abuzz with terms like DFM, DFY etc., the impact of foundry information on the EDA and IP space gained further importance.

So, are we headed towards a landscape dominated by a few major players (with deep pockets & partnerships) sporting One-Stop-Shops & dotted by smaller players excelling in niche areas say point EDA tools, special IPs ?

Bring on 2006

Mentors' CEO Walden Rhines' interview in Electronic Times (posted on 2/12/05) brought out 2 interesting points in the EDA industry :

First is on the EDA industry growth which Rhines attributes mainly to developing new solutions to new problems, developing new methodologies & applying technology to different applications. With a very small growth in the number of designers and with tools and methodology in place, design companies do not tend to spend so much in purchasing that many new licenses/seats.

The second interesting point is about start-ups. Usually started by professionals from the major EDA companies/design companies when they see issues/loops in the design flow which they feel they can plug in much better than the existing tools. With the market growing more and more towards point tools and now towards an open platform, they focus on a niche issue. While they contribute a little over 20% of the market revenue, they do represent a major chunk of the EDA methodologies mindshare. And excepting a few of them who have a solid business plan in addition to the strong technology base, most get acquired by the major EDA companies - and spur their growth.

Cisco turns to ZTE in China

While most other competitors foresee more growth in China, Cisco sees an edge in India and is investing heavily there. The things going for India include an unregulated economy, less competitive environment & a growing market . It’s worries in China include weaker IP protection laws and an edge to home grown local companies like Huawei, Harbor Networks etc. through loans and government support.

The Cisco-ZTE co-operation agreement will let Cisco take advantage of ZTE’s position in the local service provider market and it’s customer knowledge.

More on DFM....

I read this paper, “Yield challenges require new DFM approach” by P.T Patel in EE Times. It’s very well written and informative.

Yet another pointer to making the existing design tools (the focus in the article was on routing) more suitable for getting your design manufacturable.

Can someone explain DFM ?

Quite an interesting article in Electronic Engineering Times by Richard Goering.

Getting to basics ….

In commercial space, a designer designs a chip with the objective that it should not only function as per specs but also be manufactured in a commercially viable mode. This is implicit. Else shouldn’t we have heard about tools like Design for Silicon Success/DFSS or DFFTSS….??

Yes, we do have flows which aim for FTSS but not point tools. The point tools facilitate various design phases like simulation, synthesis, routing etc. but it’s a design flow which optimizes their usage to achieve objectives like intended functionality , high yield. In fact, all the existing design tools should have this “DFM” embedded in them by default.

Designers need not become manufacturing experts and the tools should be good enough to handle the yield issues in a transparent and automatic manner. But with the mandatory breaking of walls between design and manufacturing in the DSM zone, it does help for the designer to be aware of the potential manufacturing issues and take them into account while designing in order to avoid corrections at later stages.

Is Infineon going fabless ?

One of the potential solutions in addressing the challenges in manufacturing sub 90nm is in greater collaboration. How many of the existing top semiconductor companies can afford to be profitable while keeping their legs in both chip design as well as optimal yield DSM manufacturing ? One needs to focus upon ones’ strengths while leveraging with ones’ partners on others. Partnerships are extending; it’s a need & not just an option.

It makes me reflect on an article posted in Silicon Strategies on 12/27/2004, “15 predictions for IC, equipment biz in 2005 and beyond” which had a compilation of 15 predictions for the IC and chip-equipment industries in 2005 and beyond and listed some foundry marriages.

The sifting is being done……..

Unshackled IBM Microelectronics savors Game Box wins

Unshackled IBM Microelectronics savors Game Box wins - a very interesting article by Ed Sperling in a special report, Movers & Shakers 2005, in Electronic Business online.

Lining up 3 top gaming platforms, Sony PlayStation 3, Microsoft Xbox 360 and the follow on to the Nintendo GameCube as customers for it’s Cell Processor is a real volume play. In the absence of any real killer application, high volumes design wins do not come easy.

Steven Longoria, vice president of semiconductor technology platforms in IBM's Systems and Technology Group mentions that getting it’s technology consistent to avoid repetition of development steps is IBM’s top priority.

This is one area in the industry which usually takes a backseat amongst other priorities and is a major cause of ASIC design re spins. With the high mask costs, FTSS is getting more & more significant thus putting an ASIC vendor with a good track record of FTSS higher on the ASIC clients’ list. The shrinking market windows also do not leave much room for re spins.

Indian design activity on fast track, says iSuppli

Market research company, iSuppli Corp noted in a recent article posted in Electronic Engineering Times by Peter Clarke that India’s semiconductor design industry will nearly triple by 2010; it’s predicted to be 624M$ in ’05.

Investment in India needs to be for a long term strategic reason. Companies jumping into the bandwagon solely for cost reduction will most likely lose out. Some of the very factors driving the growth of the semiconductor industry here e.g. low cost design talent, strong education infrastructure and rapidly growing local market lead to challenges like high attrition rate. While money is a major factor for employee retention, career growth conducive work environment with interesting & innovative work on latest technology will help.

The other challenge of lack of trained designers is being addressed by the industry along with academia leading to several training start-ups which deliver mid & short term courses for fresh engineering graduates as well as working executives for VLSI careers.

Panelists ponder challenges at 45 nm

The volumes need to justify the high costs involved in 45 nm. Costs include the mask cost (with 2 M$ not being ruled out), design challenges, variability & yield issues to count a few. The consumer market is the major drive for cost reduction and high volumes. However, it needs to be kept in mind that the market windows in this segment are shrinking. To capitalize on these high volumes, chip vendors need to be nimble enough to get the 45 nm product out in time – a feat which is getting tougher as one scales down in the DSM zone.

As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.

Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.

No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.

Excessive guardbanding should not cut back the gains arising from the scaling to this technology.

As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..

Moore's Law

The microelectronics industry owes much to Moore’s Law – the number of transistors on a chip double every 2 years. It’s a principle which has been solid and consistent for the last 3 decades.

In an article posted by Bill Roberts in Electronic Business, Satoru Ito, CEO of Renesas Technology says. "Because of Moore's Law, the industry has had a common road map for technological innovation. This allows partnerships and planning for investment."

It’s an economic barometer with geometric scaling transforming to economic scaling.

Moore’s Law has led to partnership. For no single entity, no matter how deep it’s pockets are and how well entrenched it is with brain power, can work out on it’s own the complexities in the microelectronics ecosystem paved by this law.

It has led to specialization. Semiconductor equipment materials, foundries, EDA, Contract manufacturing, IPs, yield management processes – it has spawned them all. It has spurred entrepreneurial culture without which technology’s potential could not have been realized. And with specialization and innovation not recognizing any geographical boundaries, it has further led to globalization. Biz interests make you go where there is infrastructure, cost saving, brain power, innovation – strategy reason. Moore’s law has sustained because it’s driven by pure economics. Geometric scaling is a prelude to diminishing the cost.

And it has also led to the omnipresent question - after Moore's Law, what ???

India to take stake in fab project

It’s heartening to note Indian government’s proactive stance in putting India’s footprint on the hardware arena too. Several multinationals have a design/R&D setup in India. While most initially came for the comparatively cheap manpower, they’ve stayed put for the brain power and are now investing for innovation. Several local services and product companies too have sprung up. But what has been lacking is an efficient semiconductor manufacturing base i.e. fabs & testing entities. Developing and sustaining them is a formidable task as it’s an extremely capital (& commitment) intensive zone.

Taiwan’s ITRI is a good example to follow in guiding the technological and economic growth of the country. ITRI lists establishing new High tech industry, upgrading traditional industries, leading the drive for sustainable growth and developing highly skilled human resources under their industrial impact. It has played a vital role in turning this island state into a semiconductor hub housing world’s top two foundries and boasting of highly skilled designers.

IBM backs VCs, startups to pursue platform aims

IBMs’ VC Group’s strategy outlines a varying and rewarding approach to the functioning of a ventures capital arm of a large company. Deviating from the well trodden path of investing cash for ROI, it is emphasizing more on relationships, interests’ alignment and development of a mutually supported ecosystem.

As IBM Corp. VP & MD of it’s VC group, Claudia Fan Munce, stresses in an article in EE Times, the access IBM gains to companies in emerging technos and geographies is worth much more than the return on the cash itself. IBM’s involvement with VC firms and startups aids it in setting it’s technology agenda and pushing it through.

Especially in Asian countries where the right networking/connections building (or guanxi as is called in Chinese) is so important for biz growth, this strategy looks more effective than the relatively “cold” dollars vs return.

Consumer Era gives birth to "Gigafabs"

With consumer electronics joining PCs and internet based communications as a major semiconductor industry driver, fabs are getting into another league – Gigafabs. TSMC’s Mark Liu differentiates between the fabs on the basis of monthly wafers capacity – 80 to100K qualify as gigafabs while megafabs have a run rate of 50k wafers.

Consumer electronics market has a very short market window including a steep ramp up and leaves little room for redesigns. High price elasticity ranges encompass some real high priced niche products on one end and basic generic commodity tagged products on the other – and both categories can lead to massive volumes if the timing/placing-features-price combo target is hit.

Gigafabs help here because no vendor would like to be placed in a position where he has hit the market with the right product at the right time only to run out of fab capacity – a major biz opportunity loss. Also chips produced cheaper in the fabs (an advantage of gigafabs) can be sold cheaper. While gigafabs help to spread out the costs, not all players can join in due to the high costs involved.

Warner to back Blu-ray and HD-DVD format

The latest in the battle for the new high definition DVD standard – Warner to back Blu-ray and HD-DVD format. Warner Bros. Entertainment, till now a key HD-DVD backer among the Hollywood studios announced that it’ll release films on Blu-ray format too.

The recent issue of Business Week has a very well written article giving the synopsis of the struggles in this standard.

The key entities in this format war are:
A. Consumer Electronics
1. Sony has a lot at stake in this standard. It’s a triple gain for them if Blu-ray becomes the industry format:
- Royalties from sale of all the Blu-ray disks sold
- Resurgence in it’s movie biz through DVD sales
- High sales in electronic gear (HDTVs, movie cameras, Blu-ray optical drives and most importantly – it’s new PlayStation game consoles which will include a Blu-ray drive for playing movies

2. Toshiba would like to continue the inflow of royalty payments coming from it’s current DVDs through it’s HD-DVD patents.

3. Others : HDTV and DVD drive makers

B. Media
With Warner supporting Blu-ray format too, the Sony camp has now 5 of 6 film studios. Sony’s safeguards developed to prevent Blu-ray movies from being ripped to a computer’s hard drive strengthened support for it’s format from the studios.

C. PC industry
1. Microsoft, Intel : They stand a lot to gain if PC were to emerge as a hub for digital entertainment. Microsoft has an additional issue – game console war with Sony. While Microsoft had decided to hold down costs by not including a next generation DVD player in the Xbox console (and instead stream HD content from a PC to a console which could be attached to a TV), Sony said that it’ll include Blu-ray in the next PlayStation game console beginning next year. Plus it decided not to use Microsoft’s iHD technology to add interactive features to Blu-ray disks, opting instead for Java based technology. Microsoft says that Blu-rays disks will be more expensive to manufacture; others do not see any big cost difference.
Both Microsoft and Intel back Toshiba’s HD-DVD format.

2. Dell, HP, Apple: They back Blu-ray. Dell and HP sell HDTVs too.
In an attempt to bridge the gap between the two formats, HP has recently urged the other Blu-ray members to support 2 key technologies (currently supported in HD-DVD): Managed Copy (lets users make legitimate copies of their HD movies) and iHD (Microsoft’s techno for interactive features).

There looks to be only 1 winner.........

Design trends & EDA tools : China & Taiwan

I recently read the latest report from EE Times and Gartner Dataquest on Design Trends & EDA Tools : China & Taiwan. It can be accessed from their website http://www.eetasia.com.

The report makes a very interesting reading and made me ponder on a few points.......

ASIC Design segment

A. Application segment
While consumer applications remained the major application segment in Taiwan (as was in ’04 too), it displaced Telecom/Datacom in China to be the major one there too. Some possible underlying reasons (apart from generic market conditions) could be
· Telecom/Datacom designs have traditionally been using the leading edge process geometry. The rising mask costs associated with them could have been a factor of the decrease in new ASIC designs.
· The varied & vast set of categories within the consumer applications mkt. abets more ASIC designs and spin-offs.
· More consumer ASICs are coming out with the rapid growth of the China consumer mkt.

B. Gate Count
The general increase in the gate count follows the rising complexity which is also aided by the integration of various functions/categories in a single product.
Majority of the respondents working on large designs are companies that are local subsidiaries of foreign companies or local ventures – not joint ventures with foreign companies. This is mostly due to the high costs involved in large & complex designs. It makes sense for joint ventures with foreign companies to focus on the local marketing & enhance their foreign partner’s footprint in the local mkt.

C. Process Geometry
China figures indicate a more rapid embracing of newer technos.
The 0.18um in Taiwan, apart from remaining the predominant node for the past 3 years, has grown from 35% from last year to 44% while the 0.13um has increased from 13% to 23%.
0.18um is still the dominant node in China. However, it’s share has slightly decreased from 49% to 45%. But it’s in the 0.13um that we see the real increase – 12% to 31%

D. IP core usage rate
EDA companies’ share has decreased and has been correctly attributed to their partnering with foundries. With the increasing complexities and the focus going more towards Design for Yield, it is natural for foundries to play a major role in this partnership with EDA vendors/3rd party IP suppliers. The growing complexity of selecting the right IP & the subsequent issues seen during their integration in the design compel companies resort to developing them in-house. The marked surge in the independent 3rd party suppliers is also due the fact that they specialize in their niche IPs & these IPs are their main products.

EDA tools usage
Increasing reliability and reduced costs are the paramount factors for the electronic designers in Taiwan (increased functionality is no longer the most important goal) while increased functionality and reduced cost are the most important goals for the designers in China.

This possibly indicates a more mature market (in terms of EDA tools usage) in Taiwan where they seem to be more conversant and satisfied with the various functionality features offered by the EDA tools and hence are focusing more on reliability i.e. fewer issues while going through the design flow and hence shortening their time to market.
Cost reduction remains common; not surprising where Consumer applications is the predominant market.

Will Structured ASICs be successful ?

Comments on the above article (written by Vince Hopkins in Electronic News)........

Tweak a bit here and there for it’s derivatives, term it in various categories, yes, the bottom line is identical value propositions i.e. reduced NRE and faster time to market which have become critical factors in the transient markets and DSM technos.

So, one has variants: a 90% ready netlist which at least in concept can readily accept limited design changes as per multiple customer requirements and drastically reduce the design cycle time to semi fabricated design slices ready for custom metallization for final customer designs.

ASIC vendors providing both traditional ASIC (cell based) and Structured ASIC capabilities hold an added advantage for the customer if he does decide to transit later from structured to regular ASIC i.e. for higher volumes with cost reduction. Filling the gap of the mid range market, it’s given another option for customers sitting on the FPGA/ASIC fence.