India outlines long awaited IC policy

After several hiccups, India has announced its IC policy.

Dubbed the Special Incentive Package Scheme, the initiative is focused on attracting investments for setting up semiconductor plants and other technology manufacturing industries. Semiconductor companies seeking incentives—which will be 20 percent of the capital expenditure during the first 10 years—will have to invest a minimum $550 million, according to the plan.

The salient points were announced Feb. 22 with details to be out in the coming two weeks in a document that spells out the specifics about the level of equity, the interest-free component and other financial details.

This announcement is most likely to be followed by announcements by potential investors. AMD has already announced a technology pact with SemIndia Inc. for a semiconductor manufacturing facility in Hyderabad.

At least two more semiconductor manufacturing facilities are expected to be announced in the next few weeks, according to Raj Khare, chairman, India Semiconductor Association.
Samsung, Freescale, Motorola, Intel, Infineon, STMicrorelectronics and Toshiba are among the possible investors in a Rs.20,394 crore ($4.5 billion) manufacturing facility being set up by the Hindustan Semiconductor Manufacturing Corp. (HSMC) which is expected to establish a fabrication complex that will include several foundries to be built by HSMC. The fabs will 200- and 300mm wafer lines.

It has to be seen if and how the various consortiums as well as companies like Intel etc. tread on this “red carpet” rolled out by the Indian govt. And having decided to tread, it has to be seen which technology direction will these new fabs take up (as noted in my earlier post, “Vision Summit explores strategies driving semicon industry growth”)

Blaze DFM merges with Aprio

So, the DFM consolidation has begun…..

While acquisitions of DFM companies by EDA vendors was already there, this is the first merger between 2 DFM companies. Blaze’s parametric DFM expertise complements Aprio’s lithography analysis skill-set. Together they can synergize on DFM analysis as well as optimization and address both manufacturing as well as the designer sets.

I had pointed out in an earlier post “Who will be left standing in DFM”, that in the consolidation phase, it will be a selected few who stand a chance to survive. Together, Blaze DFM-Aprio do come under this category.

Will this serve as the catalyst for further such mergers and pave way for “pure play DFM vendors” as opposed to EDA vendors selling DFM as a part of their “complete design flow portfolio” ??

NEC exits Structured ASIC market

Yet another company exits the Structured ASIC arena. After LSI Logic and then Synplicity, it’s now the turn of NEC. This is in line with a string of closures/layoffs and policy changes announced by Mr. Nakajima, NEC’s president.

NEC feels that Structured ASICs have not grown to a big biz yet and is risky to invest large resources in it. This is further aggravated when the company itself is not doing well overall.

Why is it that Structured ASICs hasn’t caught on? The general thinking when Structured ASICs evolved was that as long as there is the issue of high NREs and long design cycle time compounded by increasing risks involved with new designs/new techno/short market window etc., there will be a need to address the gap between FPGAs and Cell based ASICs. Structured ASICs definitely address this gap.

Could a possible reasoning be in the marketing strategy of Structured ASICs ??? As some one had pointed out a few years back……”Most of the companies that make structured ASIC products made their real money from cell-based ASIC lines. With FPGA companies eating into their profits from the bottom, they rolled out structured ASIC lines in retaliation. Their natural instinct, then, was to position these products directly against FPGAs. The problem with that positioning is that structured ASICs make a much more compelling solution when compared with cell-based products. Since most structured ASIC lines' lowest density is close to the highest density available in FPGA, there really isn't much overlap between single FPGAs and single structured ASICs. A structured ASIC is a good replacement for a two-or-more FPGA system, but the one-to-one replacement isn't often an option. Against cell-based designs, however, structured ASICs are stellar. They have much shorter design cycles, an order of magnitude lower NRE, much lower design tool costs, significantly less expertise required for success, and very competitive performance, density, power, and unit cost. The marketing mavens at these companies are understandably reluctant to launch an all-out assault on their own revenue generators, however, so they have put together campaigns that probably confused the customer more than they promoted this very compelling technology”

Grading of India's semicon industry

ISA-Ernst & Young, India’s recently released report presents a snapshot of India’s semicon industry.
Some of the salient points are:
Talent quality: Moderate (US rated very high)
Talent Availability & scalability: Very Well (4th amongst peers, US rated 3rd )
Technical education quality: Moderate (rated 5th, US rated very high)
Talent cost advantage: Very well (Best along with China, US rated lowest)
Peer countries selected for study: Canada, China, Czech Republic, India, Israel, Taiwan, the United Kingdom and the United States

Other than the more prevalent known aspects as cited above, the report underscored a few interesting and vital points:
- India’s need to conceptualize & build products and move up the value chain
- Relatively lower level of electronics manufacturing which adversely impacts the semicon market potential
- Need to increase IP registration

Statistical tool avoids overdesign with excessive margins

A new tool in the DFM arena –

Solido Design Automation has announced a tool for transistor level statistical design & verification. Unlike most of the DFM touted tools in the market, this one is to be used by designers prior to layout.

It promises 5 basic capabilities –
1. Statistical sampling that describes how processes can vary so that circuit simulators can estimate possible outputs.
2. Tradeoff analysis that lets users adjust specifications to impact yield
3. Statistical characterization, that shows the user how to improve the design to make it more robust to process variations.
4. Statistical circuit enhancement that automatically optimizes designs by sizing transistors.
5. Statistical visualization lets users explore and view the data.

Looks like a comprehensive set….

Post-silicon debugging worth a second look

With verification consuming up to 70% of design effort and debug up to 50% of that time (this means up to 35% of overall design time is spent understanding how a design works or why it doesn't!) - I share Richard Goering’s musing that it’s a wonder that EDA vendors have paid little attention to post-silicon debug.

Post-silicon validation being a confrontational sale may be a significant hurdle for selling wares in this space. However another not so insignificant fact is that post-silicon validation is done in 2-3 phases – first on standalone chip, then on the system and then the field trials. The latter two being heavily dependant on applications and the working environment pose too many variables in the debug process and it is not an easy task to implement all these in a tool. Nevertheless it is a fact that good solutions in this space will be a boon to the chip designer (not to say the S&M guys who keep their fingers crossed while awaiting reports of field tests and subsequently news on the 1st order…)

Vision Summit explores strategies driving semicon industry growth

A couple of contrasting views over the fab technology direction that India should follow was reported from the ISA Vision Summit 2007. While one view stated that it’ll be prudent for India to initially establish manufacturing capacities in older technologies and address those requirements which are not addressed by the more competitive larger multinational companies. Else it will fall prey to overcapacity problem.

A conflicting view presented some of the alternate views of addressing the overcapacity situation. In India’s case, it can be by focusing on technologies which are driven by applications of the products required by the local market i.e. applications are the fab techno drivers and not any predetermined process geometry.

Who will be left standing in DFM?

An interesting exchange of ideas reported in Electronics News recently.

DFM is the bridge between design and manufacturing. Most of the tools in the DFM arena are now towards the manufacturing side i.e. improving OPC while a selected few are focusing on the design part of the bridge. I agree with the viewpoint that in the consolidation phase, it will be these selected few who stand a chance to survive. Moving from binary rules based info to distribution information coming from manufacturing is not a smooth transition…..

TSMC sets up office in India

TSMC has announced the opening up of its office in Bangalore, India with the primary mission of supporting its existing customers with design activities in India. They see a huge increase in the number of advance technology designs coming from India.

What surprises me is their delay till date. With no major advance tech fab in the country, delays in fab investments/policies and spurt of fabless design companies, there had long been the potential of strengthening biz thru local presence.

Cadence deploys CPF

Cadence has deployed CPF (Common Power Format) into its existing tools. Rather than making it available as a special feature in tools that would have to be paid for separately, Cadence has made most of its existing tools CPF compliant.

While this makes it more convenient for the user on one hand, he expresses the design power intent/requirements just once and then the system/design flow takes care of the rest, it provides a potential blocking factor for user should the industry embrace an alternate power format (UPF or a third one).

However, Cadence has said, "Wherever the industry takes CPF and UPF, if the users want it, we'll do it. If you're a Cadence customer, as of now, the power standards thing is over. Go make chips. Whether it's CPF or UPF or some common thing in the future doesn't matter any more. We've got the software system that will build the chips, and we'll follow wherever the standard goes."

Let’s see what follows from the rival potential standard’s camp……